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| september 1998 1/70 rev. 2.6 st62t00c/t01c st62t03c/e01c 8-bit otp/eprom mcus with a/d converter, oscillator safeguard, safe reset and 16 pins n 3.0 to 6.0v supply operating range n 8 mhz maximum clock frequency n -40 to +125c operating temperature range n run, wait and stop modes n 5 interrupt vectors n look-up table capability in program memory n data storage in program memory: user selectable size n data ram: 64bytes n user programmable options n 9 i/o pins, fully programmable as: C input with pull-up resistor C input without pull-up resistor C input with interrupt generation C open-drain or push-pull output C analog input (except st62t03c) n 3i/o lines can sink up to 20ma to drive leds or triacs directly n 8-bit timer/counter with 7-bit programmable prescaler n digital watchdog n oscillator safe guard n low voltage detector for safe reset n 8-bit a/d converter with up to 4 analog inputs n on-chip clock oscillator can be driven by quartz crystal ceramic resonator or rc network n power-on reset n one external non-maskable interrupt n st626x-emu2 emulation and development system (connects to an ms-dos pc via a parallel port) device summary (see end of datasheet for ordering information) pdip16 pso16 cdip16w device otp (bytes) eprom (bytes) i/o pins analog inputs st62t00c 1036 - 9 4 ST62T01C 1836 - 9 4 st62t03c 1036 - 9 none st62e01c - 1836 9 4 17
2/70 table of contents 70 document page 18 st62t00c/t01c/st62t03c/e01c . . . . . . . . . . . . . . . . . . . . . . . 1 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3.2 program space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3.3 data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3.4 stack space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3.5 data window register (dwr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4 programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.4.1 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.4.2 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.4.3 eprom erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 clocks, reset, interrupts and power saving modes . . . . . . . . . . . . . . . . . . . . . 14 3.1 clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1.1 main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1.2 low frequency auxiliary oscillator (lfao) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1.3 oscillator safe guard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.1 reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 3.2.2 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.3 watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.4 lvd reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.5 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.6 mcu initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3 digital watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3.1 digital watchdog register (dwdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3.2 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4.1 interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4.2 interrupt procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.4.3 interrupt option register (ior) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.4.4 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.5 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 3.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.5.3 exit from wait and stop modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.1 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.1.1 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.1.2 safe i/o state switching sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.1.3 i/o port option registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3/70 table of contents document page 19 4.1.4 i/o port data direction registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.1.5 i/o port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.2 timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.2.1 timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.2.2 timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.2.3 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.2.4 timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 9 4.3 a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.3.1 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5 software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.1 st6 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.2 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.3 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.3 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.4 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.5 a/d converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.6 timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7 general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.2 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 st62p00c/p01c/p03c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 1.2 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 1.2.1 transfer of customer code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 1.2.2 listing generation and verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 st6200c/01c/03c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 1.2 rom readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 1.3 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 1.3.1 transfer of customer code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 1.3.2 listing generation and verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4/70 st62t00c/t01c st62t03c/e01c 1 general description 1.1 introduction the st62t00c,t01c,t03c and st62e01c de- vices are low cost members of the st62xx 8-bit hcmos family of microcontrollers, which is target- ed at low to medium complexity applications. all st62xx devices are based on a building block ap- proach: a common core is surrounded by a number of on-chip peripherals. the st62e01c is the erasable eprom version of the st62t00c,t01c,t03c and device, which may be used to emulate the st62t00c,t01c and t03c device, as well as the respective st6200c,01c and 03c rom devices. otp and eprom devices are functionally identi- cal. the rom based versions offer the same func- tionality selecting as rom options the options de- fined in the programmable option bytes of the otp/eprom versions. otp devices offer all the advantages of user pro- grammability at low cost, which make them the ideal choice in a wide range of applications where frequent code changes, multiple code versions or last minute programmability are required. these compact low-cost devices feature a timer comprising an 8-bit counter and a 7-bit program- mable prescaler,an 8-bit a/d converter with up to 4 analog inputs and a digital watchdog timer, making them well suited for a wide range of auto- motive, appliance and industrial applications. figure 1. block diagram test nmi interrupt program 1836 bytes pc stack level 1 stack level 2 stack level 3 stack level 4 stack level 5 stack level 6 power supply oscillator reset data rom user selectable data ram 64 bytes port a port b timer digital 8 bit core test/v pp (ST62T01C, e01c) 8-bit a/d converter pa1..pa3 (20ma sink) v dd v ss oscin oscout reset watchdog : memory pb0..pb1 1036 bytes (st62t00c,t03c) (*) analog input availability depend on versions pb3,pb5..pb7 / ain (*) 20 5/70 st62t00c/t01c st62t03c/e01c 1.2 pin descriptions v dd and v ss . power is supplied to the mcu via these two pins. v dd is the power connection and v ss is the ground connection. oscin and oscout. these pins are internally connected to the on-chip oscillator circuit. a quartz crystal, a ceramic resonator or an external clock signal can be connected between these two pins. the oscin pin is the input pin, the oscout pin is the output pin. reset . the active-low reset pin is used to re- start the microcontroller. internal pull-up is provid- ed at this pin. test/v pp . the test must be held at v ss for nor- mal operation. if test pin is connected to a +12.5v level during the reset phase, the eprom programming mode is entered. nmi. the nmi pin provides the capability for asyn- chronous interruption, by applying an external non maskable interrupt to the mcu. the nmi input is falling edge sensitive. the user can select as op- tion the availability of an on-chip pull-up at this pin. pa1-pa3. these 3 lines are organized as one i/o port (a). each line may be configured under soft- ware control as inputs with or without internal pull- up resistors, interrupt generating inputs with pull- up resistors, open-drain or push-pull outputs. pa1- pa3 can also sink 20ma for direct led driving. pb0..pb1,pb3,pb5-pb7. these 6 lines are or- ganized as one i/o port (b). each line may be con- figured under software control as inputs with or without internal pull-up resistors, interrupt generat- ing inputs with pull-up resistors, open-drain or push-pull outputs. pb3,pb5..-pb7 can be used as analog inputs for the a/d converter on the st62t00c, t01c and e01c. figure 2. st62t03c,t00c, t01c, and e01c pin configuration 1 2 3 4 5 6 7 8 11 12 13 14 15 16 v dd oscin oscout nmi v pp /test reset ain*/pb7 ain*/pb6 v ss pa1/20 ma sink pa2/20 ma sink pa3/20 ma sink pb0 pb1 pb3/ain* pb5/ain* *analog input availability depend on device 10 9 21 6/70 st62t00c/t01c st62t03c/e01c 1.3 memory map 1.3.1 introduction the mcu operates in three separate memory spaces: program space, data space, and stack space. operation in these three memory spaces is described in the following paragraphs. briefly, program space contains user program code in otp and user vectors; data space con- tains user data in ram and in otp, and stack space accommodates six levels of stack for sub- routine and interrupt service routine nesting. figure 3. memory addressing diagram program space program interrupt & reset vectors accumulator data ram bank select window select ram x register y register v register w register data read-only window ram / eeprom banking area 000h 03fh 040h 07fh 080h 081h 082h 083h 084h 0c0h 0ffh 0-63 data space 0000h 0ff0h 0fffh memory memory data read-only memory 22 7/70 st62t00c/t01c st62t03c/e01c memory map (contd) 1.3.2 program space program space comprises the instructions to be executed, the data required for immediate ad- dressing mode instructions, the reserved factory test area and the user vectors. program space is addressed via the 12-bit program counter register (pc register)program memory protection. the program memory in otp or eprom devices can be protected against external readout of mem- ory by selecting the readout protection op- tion in the option byte. in the eprom parts, readout protection option can be disactivated only by u.v. erasure that also results into the whole eprom context erasure. note: once the readout protection is activated, it is no longer possible, even for stmicroelectronics, to gain access to the otp contents. returned parts with a protection set can therefore not be ac- cepted. figure 4. program memory map (*) reserved areas should be filled with 0ffh 0000h 0affh 0b00h 0b9fh not implemented reserved * user program memory (otp) 1024 bytes 0ba0h 0f9fh 0fa0h 0fefh 0ff0h 0ff7h 0ff8h 0ffbh 0ffch 0ffdh 0ffeh 0fffh reserved * reserved interrupt vectors nmi vector user reset vector 0000h 07ffh 0800h 087fh not implemented reserved * user program memory (otp/eprom) 1824 bytes 0880h 0f9fh 0fa0h 0fefh 0ff0h 0ff7h 0ff8h 0ffbh 0ffch 0ffdh 0ffeh 0fffh reserved * reserved interrupt vectors nmi vector user reset vector st62t03c,t00c ST62T01C, e01c 23 8/70 st62t00c/t01c st62t03c/e01c memory map (contd) 1.3.3 data space data space accommodates all the data necessary for processing the user program. this space com- prises the ram resource, the processor core and peripheral registers, as well as read-only data such as constants and look-up tables in otp/ eprom. 1.3.3.1 data rom all read-only data is physically stored in program memory, which also accommodates the program space. the program memory consequently con- tains the program code to be executed, as well as the constants and look-up tables required by the application. the data space locations in which the different constants and look-up tables are addressed by the processor core may be thought of as a 64-byte window through which it is possible to access the read-only data stored in otp/eprom. 1.3.3.2 data ram in st6200c/01c/03c devices, the data space in- cludes 60 bytes of ram, the accumulator (a), the indirect registers (x), (y), the short direct registers (v), (w), the i/o port registers, the peripheral data and control registers, the interrupt option register and the data rom window register (drw regis- ter). 1.3.4 stack space stack space consists of six 12-bit registers which are used to stack subroutine and interrupt return addresses, as well as the current program counter contents. table 1. st6200c/01c/03c data memory space reserved 000h 03fh data rom window area 64 bytes 040h 07fh x register 080h y register 081h v register 082h w register 083h data ram 60 bytes 084h 0bfh port a data register 0c0h port b data register 0c1h reserved 0c2h reserved 0c3h port a direction register 0c4h port b direction register 0c5h reserved 0c6h reserved 0c7h interrupt option register 0c8h* data rom window register 0c9h* reserved 0cah 0cbh port a option register 0cch port b option register 0cdh reserved 0ceh reserved 0cfh a/d data register(except st62t03c) 0d0h a/d control register (except st62t03c) 0d1h timer prescaler register 0d2h timer counter register 0d3h timer status control register 0d4h reserved 0d5h 0d6h 0d7h watchdog register 0d8h reserved 0d9h 0feh accumulator 0ffh * write only register 24 9/70 st62t00c/t01c st62t03c/e01c memory map (contd) 1.3.5 data window register (dwr) the data read-only memory window is located from address 0040h to address 007fh in data space. it allows direct reading of 64 consecutive bytes locat- ed anywhere in program memory, between ad- dress 0000h and 0fffh (top memory address de- pends on the specific device). all the program memory can therefore be used to store either in- structions or read-only data. indeed, the window can be moved in steps of 64 bytes along the pro- gram memory by writing the appropriate code in the data window register (dwr). the dwr can be addressed like any ram location in the data space, it is however a write-only regis- ter and therefore cannot be accessed using single- bit operations. this register is used to position the 64-byte read-only data window (from address 40h to address 7fh of the data space) in program memory in 64-byte steps. the effective address of the byte to be read as data in program memory is obtained by concatenating the 6 least significant bits of the register address given in the instruction (as least significant bits) and the content of the dwr register (as most significant bits), as illustrat- ed in figure 5 below. for instance, when address- ing location 0040h of the data space, with 0 load- ed in the dwr register, the physical location ad- dressed in program memory is 00h. the dwr reg- ister is not cleared on reset, therefore it must be written to prior to the first access to the data read- only memory window area. data window register (dwr) address: 0c9h write only bits 6, 7 = not used. bit 5-0 = dwr5-dwr0: data read-only memory window register bits. these are the data read- only memory window bits that correspond to the upper bits of the data read-only memory space. caution: this register is undefined on reset. nei- ther read nor single bit instructions may be used to address this register. note: care is required when handling the dwr register as it is write only. for this reason, the dwr contents should not be changed while exe- cuting an interrupt service routine, as the service routine cannot save and then restore the registers previous contents. if it is impossible to avoid writ- ing to the dwr during the interrupt service routine, an image of the register must be saved in a ram location, and each time the program writes to the dwr, it must also write to the image register. the image register must be written first so that, if an in- terrupt occurs between the two instructions, the dwr is not affected. figure 5. data read-only memory window memory addressing 70 - - dwr5 dwr4 dwr3 dwr2 dwr1 dwr0 data rom window register contents data space address 40h-7fh in instruction program space address 765432 0 543210 543210 read 1 6 7 8 9 10 11 01 vr01573c 12 1 0 data space address : : 59h 0 0 0 0 1 00 1 1 1 example: (dwr) dwr=28h 11 000 00 00 1 rom address:a19h 11 13 01 25 10/70 st62t00c/t01c st62t03c/e01c 1.4 programming modes 1.4.1 option bytes the two option bytes allow configuration capabili- ty to the mcus. option bytes content is automati- cally read, and the selected options enabled, when the chip reset is activated. it can only be accessed during the programming mode. this access is made either automatically (copy from a master device) or by selecting the option byte programming mode of the pro- grammer. the option bytes are located in a non-user map. no address has to be specified. eprom code option byte (lsb) eprom code option byte (msb) d15-d11. reserved. must be cleared d10. reserved. must be set to 1. extcntl. external stop mode control . . when extcntl is high, stop mode is available with watchdog active by setting nmi pin to one.. when extcntl is low, stop mode is not available with the watchdog active. lvd. lvd reset enable. when this bit is set, safe reset is performed by mcu when the supply voltage is too low. when this bit is cleared, only power-on reset or external reset are active. protect . readout protection. this bit allows the protection of the software contents against piracy. when the bit protect is set high, readout of the otp contents is prevented by hardware.. when this bit is low, the user program can be read. oscil . oscillator selection . when this bit is low, the oscillator must be controlled by a quartz crys- tal, a ceramic resonator or an external frequency. when it is high, the oscillator must be controlled by an rc network, with only the resistor having to be externally provided. d5. reserved. must be cleared to zero. d4. reserved. must be set to one. nmi pull. nmi pull-up . this bit must be set high to configure the nmi pin with a pull-up resistor. when it is low, no pull-up is provided . d2. reserved. must be set to 1. wdact . this bit controls the watchdog activation. when it is high, hardware activation is selected. the software activation is selected when wdact is low. osgen . oscillator safe guard . this bit must be set high to enable the oscillator safe guard. when this bit is low, the osg is disabled. the option byte is written during programming ei- ther by using the pc menu (pc driven mode) or automatically (stand-alone mode) 70 pro- tect oscil - - nmi pull -wdact os- gen 15 8 ------ extc- ntl lvd 26 11/70 st62t00c/t01c st62t03c/e01c programming modes (contd) 1.4.2 program memory eprom/otp programming mode is set by a +12.5v voltage applied to the test/v pp pin. the programming flow of the st62t00c,t01c,t03c and e01c is described in the user manual of the eprom programming board. table 2. st62t00c, t03c program memory map table 3. ST62T01C,e01c program memory map note : otp/eprom devices can be programmed with the development tools available from stmi- croelectronics (st62e2x-epb or st622x-kit). 1.4.3 eprom erasing the eprom of the windowed package of the mcus may be erased by exposure to ultra violet light. the erasure characteristic of the mcus is such that erasure begins when the memory is ex- posed to light with a wave lengths shorter than ap- proximately 4000?. it should be noted that sun- lights and some types of fluorescent lamps have wavelengths in the range 3000-4000?. it is thus recommended that the window of the mcus packages be covered by an opaque label to prevent unintentional erasure problems when test- ing the application in such an environment. the recommended erasure procedure of the mcus eprom is the exposure to short wave ul- traviolet light which have a wave-length 2537a. the integrated dose (i.e. u.v. intensity x exposure time) for erasure should be a minimum of 30w- sec/cm 2 . the erasure time with this dosage is ap- proximately 30 to 40 minutes using an ultraviolet lamp with 12000w/cm 2 power rating. the st62e01c should be placed within 2.5cm (1inch) of the lamp tubes during erasure. device address description 0000h-0b9fh 0ba0h-0f9fh 0fa0h-0fefh 0ff0h-0ff7h 0ff8h-0ffbh 0ffch-0ffdh 0ffeh-0fffh reserved user rom reserved interrupt vectors reserved nmi interrupt vector reset vector device address description 0000h-087fh 0880h-0f9fh 0fa0h-0fefh 0ff0h-0ff7h 0ff8h-0ffbh 0ffch-0ffdh 0ffeh-0fffh reserved user rom reserved interrupt vectors reserved nmi interrupt vector reset vector 27 12/70 st62t00c/t01c st62t03c/e01c 2 central processing unit 2.1 introduction the cpu core of st6 devices is independent of the i/o or memory configuration. as such, it may be thought of as an independent central processor communicating with on-chip i/o, memory and pe- ripherals via internal address, data, and control buses. in-core communication is arranged as shown in figure 6 ; the controller being externally linked to both the reset and oscillator circuits, while the core is linked to the dedicated on-chip pe- ripherals via the serial data bus and indirectly, for interrupt purposes, through the control registers. 2.2 cpu registers the st6 family cpu core features six registers and three pairs of flags available to the programmer. these are described in the following paragraphs. accumulator (a) . the accumulator is an 8-bit general purpose register used in all arithmetic cal- culations, logical operations, and data manipula- tions. the accumulator can be addressed in data space as a ram location at address ffh. thus the st6 can manipulate the accumulator just like any other register in data space. indirect registers (x, y). these two indirect reg- isters are used as pointers to memory locations in data space. they are used in the register-indirect addressing mode. these registers can be ad- dressed in the data space as ram locations at ad- dresses 80h (x) and 81h (y). they can also be ac- cessed with the direct, short direct, or bit direct ad- dressing modes. accordingly, the st6 instruction set can use the indirect registers as any other reg- ister of the data space. short direct registers (v, w). these two regis- ters are used to save a byte in short direct ad- dressing mode. they can be addressed in data space as ram locations at addresses 82h (v) and 83h (w). they can also be accessed using the di- rect and bit direct addressing modes. thus, the st6 instruction set can use the short direct regis- ters as any other register of the data space. program counter (pc). the program counter is a 12-bit register which contains the address of the next rom location to be processed by the core. this rom location may be an opcode, an oper- and, or the address of an operand. the 12-bit length allows the direct addressing of 4096 bytes in program space. figure 6. st6 core block diagram program reset opcode flag values 2 controller flags alu a-data b-data address/read line data space interrupts data ram/eeprom data rom/eprom results to data space (write line) rom/eprom dedications accumulator control signals oscin oscout address decoder 256 12 program counter and 6 layer stack 0,01 to 8mhz vr01811 28 13/70 st62t00c/t01c st62t03c/e01c cpu registers (contd) however, if the program space contains more than 4096 bytes, the additional memory in program space can be addressed by using the program bank switch register. the pc value is incremented after reading the ad- dress of the current instruction. to execute relative jumps, the pc and the offset are shifted through the alu, where they are added; the result is then shifted back into the pc. the program counter can be changed in the following ways: - jp (jump) instructionpc=jump address - call instructionpc= call address - relative branch instruction.pc= pc +/- offset - interrupt pc=interrupt vector - reset pc= reset vector - ret & reti instructionspc= pop (stack) - normal instructionpc= pc + 1 flags (c, z) . the st6 cpu includes three pairs of flags (carry and zero), each pair being associated with one of the three normal modes of operation: normal mode, interrupt mode and non maskable interrupt mode. each pair consists of a carry flag and a zero flag. one pair (cn, zn) is used during normal operation, another pair is used dur- ing interrupt mode (ci, zi), and a third pair is used in the non maskable interrupt mode (cnmi, zn- mi). the st6 cpu uses the pair of flags associated with the current mode: as soon as an interrupt (or a non maskable interrupt) is generated, the st6 cpu uses the interrupt flags (resp. the nmi flags) instead of the normal flags. when the reti in- struction is executed, the previously used set of flags is restored. it should be noted that each flag set can only be addressed in its own context (non maskable interrupt, normal interrupt or main rou- tine). the flags are not cleared during context switching and thus retain their status. the carry flag is set when a carry or a borrow oc- curs during arithmetic operations; otherwise it is cleared. the carry flag is also set to the value of the bit tested in a bit test instruction; it also partici- pates in the rotate left instruction. the zero flag is set if the result of the last arithme- tic or logical operation was equal to zero; other- wise it is cleared. switching between the three sets of flags is per- formed automatically when an nmi, an interrupt or a reti instructions occurs. as the nmi mode is automatically selected after the reset of the mcu, the st6 core uses at first the nmi flags. stack. the st6 cpu includes a true lifo hard- ware stack which eliminates the need for a stack pointer. the stack consists of six separate 12-bit ram locations that do not belong to the data space ram area. when a subroutine call (or inter- rupt request) occurs, the contents of each level are shifted into the next higher level, while the content of the pc is shifted into the first level (the original contents of the sixth stack level are lost). when a subroutine or interrupt return occurs (ret or reti instructions), the first level register is shifted back into the pc and the value of each level is popped back into the previous level. since the accumula- tor, in common with all other data space registers, is not stored in this stack, management of these registers should be performed within the subrou- tine. the stack will remain in its deepest position if more than 6 nested calls or interrupts are execut- ed, and consequently the last return address will be lost. it will also remain in its highest position if the stack is empty and a ret or reti is executed. in this case the next instruction will be executed. figure 7. st6 cpu programming mode l short direct addressing mode vregister wregister program counter six levels stack register cz normal flags interrupt flags nmi flags index register va000423 b7 b7 b7 b7 b7 b0 b0 b0 b0 b0 b0 b11 accumulator yreg.pointer xreg.pointer cz cz 29 14/70 st62t00c/t01c st62t03c/e01c 3 clocks, reset, interrupts and power saving modes 3.1 clock system the mcu features a main oscillator which can be driven by an external clock, or used in conjunction with an at-cut parallel resonant crystal or a suita- ble ceramic resonator, or with an external resistor (r net ). in addition, a low frequency auxiliary os- cillator (lfao) can be switched in for security rea- sons, to reduce power consumption, or to offer the benefits of a back-up clock system. the oscillator safeguard (osg) option filters spikes from the oscillator lines, provides access to the lfao to provide a backup oscillator in the event of main oscillator failure and also automati- cally limits the internal clock frequency (f int ) as a function of v dd , in order to guarantee correct oper- ation. these functions are illustrated in figure 9 , figure 10 , figure 11 and figure 12 . figure 8 illustrates various possible oscillator con- figurations using an external crystal or ceramic res- onator, an external clock input, an external resistor (r net ), or the lowest cost solution using only the lfao. c l1 an c l2 should have a capacitance in the range 12 to 22 pf for an oscillator frequency in the 4-8 mhz range. the internal mcu clock frequency (f int ) is divided by 12 to drive the timer, the a/d converter and the watchdog timer, and by 13 to drive the cpu core, as may be seen in figure 11 . with an 8mhz oscillator frequency, the fastest ma- chine cycle is therefore 1.625s. a machine cycle is the smallest unit of time needed to execute any operation (for instance, to increment the program counter). an instruction may require two, four, or five machine cycles for execution. 3.1.1 main oscillator the oscillator configuration may be specified by se- lecting the appropriate option. when the crystal/ resonator option is selected, it must be used with a quartz crystal, a ceramic resonator or an external signal provided on the oscin pin. when the rc net- work option is selected, the system clock is gen- erated by an external resistor. the main oscillator can be turned off (when the osg enabled option is selected) by setting the oscoff bit of the adc control register. the low frequency auxiliary oscillator is automatical- ly started. figure 8. oscillator configurations integrated clock crystal/resonator option osg enabled option osc in osc out c l1n c l2 st6xxx crystal/resonator clock crystal/resonator option osc in osc out st6xxx external clock crystal/resonator option nc osc in osc out st6xxx nc osc in osc out r net st6xxx rc network rc network option nc 30 15/70 st62t00c/t01c st62t03c/e01c clock system (contd) turning on the main oscillator is achieved by re- setting the oscoff bit of the a/d converter con- trol register or by resetting the mcu. restarting the main oscillator implies a delay comprising the oscillator start up delay period plus the duration of the software instruction at f lfao clock frequency. 3.1.2 low frequency auxiliary oscillator (lfao) the low frequency auxiliary oscillator has three main purposes. firstly, it can be used to reduce power consumption in non timing critical routines. secondly, it offers a fully integrated system clock, without any external components. lastly, it acts as a safety oscillator in case of main oscillator failure. this oscillator is available when the osg ena- bled option is selected. in this case, it automati- cally starts one of its periods after the first missing edge from the main oscillator, whatever the reason (main oscillator defective, no clock circuitry provid- ed, main oscillator switched off...). user code, normal interrupts, wait and stop in- structions, are processed as normal, at the re- duced f lfao frequency. the a/d converter accura- cy is decreased, since the internal frequency is be- low 1mhz. at power on, the low frequency auxiliary oscilla- tor starts faster than the main oscillator. it there- fore feeds the on-chip counter generating the por delay until the main oscillator runs. the low frequency auxiliary oscillator is auto- matically switched off as soon as the main oscilla- tor starts. adcr address: 0d1h read/write bit 7-3, 1-0= adcr7-adcr3, adcr1-adcr0 : adc control register . these bits are not used. bit 2 = oscoff . when low, this bit enables main oscillator to run. the main oscillator is switched off when oscoff is high. 3.1.3 oscillator safe guard the oscillator safe guard (osg) affords drastical- ly increased operational integrity in st62xx devic- es. the osg circuit provides three basic func- tions: it filters spikes from the oscillator lines which would result in over frequency to the st62 cpu; it gives access to the low frequency auxiliary os- cillator (lfao), used to ensure minimum process- ing in case of main oscillator failure, to offer re- duced power consumption or to provide a fixed fre- quency low cost oscillator; finally, it automatically limits the internal clock frequency as a function of supply voltage, in order to ensure correct opera- tion even if the power supply should drop. the osg is enabled or disabled by choosing the relevant osg option. it may be viewed as a filter whose cross-over frequency is device dependent. spikes on the oscillator lines result in an effectively increased internal clock frequency. in the absence of an osg circuit, this may lead to an over fre- quency for a given power supply voltage. the osg filters out such spikes (as illustrated in figure 9 ). in all cases, when the osg is active, the maxi- mum internal clock frequency, f int , is limited to f osg , which is supply voltage dependent. this re- lationship is illustrated in figure 12 . when the osg is enabled, the low frequency auxiliary oscillator may be accessed. this oscilla- tor starts operating after the first missing edge of the main oscillator (see figure 10 ). over-frequency, at a given power supply level, is seen by the osg as spikes; it therefore filters out some cycles in order that the internal clock fre- quency of the device is kept within the range the particular device can stand (depending on v dd ), and below f osg : the maximum authorised frequen- cy with osg enabled. note. the osg should be used wherever possible as it provides maximum safety. care must be tak- en, however, as it can increase power consump- tion and reduce the maximum operating frequency to f osg . 70 adcr 7 adcr 6 adcr 5 adcr 4 adcr 3 osc off adcr 1 adcr 0 31 16/70 st62t00c/t01c st62t03c/e01c clock system (contd) figure 9. osg filtering principle figure 10. osg emergency oscillator principle (1) vr001932 (3) (2) (4) (1) (2) (3) (4) maximum frequency for the device to work correctly actual quartz crystal frequency at oscin pin noise from oscin resulting internal frequency main vr001933 internal emergency oscillator frequency oscillator 32 17/70 st62t00c/t01c st62t03c/e01c clock system (contd) figure 11. clock circuit block diagram figure 12. maximum operating frequency (f max ) versus supply voltage (v dd ) notes : 1. in this area, operation is guaranteed at the quartz crystal frequency. 2. when the osg is disabled, operation in this area is guaranteed at the crystal frequency. when the osg is enabled, operation in this area is guar- anteed at a frequency of at least f osg min. 3. when the osg is disabled, operation in this area is guaranteed at the quartz crystal frequency. when the osg is enabled, access to this area is prevented. the internal frequency is kept a f osg. 4. when the osg is disabled, operation in this area is not guaranteed when the osg is enabled, access to this area is prevented. the internal frequency is kept at f osg. main oscillator osg lfao m u x core : 13 : 12 : 1 timer 1 watchdog por f int main oscillator off 1 2.5 3.644.555.56 8 7 6 5 4 3 2 maximum frequency (mhz) supply voltage (v dd ) functionality is not 3 4 3 2 1 f osg f osg min guaranteed in this area vr01807 33 18/70 st62t00c/t01c st62t03c/e01c 3.2 resets the mcu can be reset in four ways: C by the external reset input being pulled low; C by power-on reset; C by the digital watchdog peripheral timing out. C by low voltage detection (lvd) 3.2.1 reset input the reset pin may be connected to a device of the application board in order to reset the mcu if required. the reset pin may be pulled low in run, wait or stop mode. this input can be used to reset the mcu internal state and ensure a correct start-up procedure. the pin is active low and features a schmitt trigger input. the internal reset signal is generated by adding a delay to the external signal. therefore even short pulses on the reset pin are acceptable, provided v dd has completed its rising phase and that the oscillator is running correctly (normal run or wait modes). the mcu is kept in the reset state as long as the reset pin is held low. if reset activation occurs in the run or wait modes, processing of the user program is stopped (run mode only), the inputs and outputs are con- figured as inputs with pull-up resistors and the main oscillator is restarted. when the level on the reset pin then goes high, the initialization se- quence is executed following expiry of the internal delay period. if reset pin activation occurs in the stop mode, the oscillator starts up and all inputs and outputs are configured as inputs with pull-up resistors. when the level of the r eset pin then goes high, the initialization sequence is executed following expiry of the internal delay period. 3.2.2 power-on reset the function of the por circuit consists in waking up the mcu by detecting around 2v a dynamic (rising edge) variation of the vdd supply. at the beginning of this sequence, the mcu is configured in the reset state: all i/o ports are configured as inputs with pull-up resistors and no instruction is executed. when the power supply voltage rises to a sufficient level, the oscillator starts to operate, whereupon an internal delay is initiated, in order to allow the oscillator to fully stabilize before execut- ing the first instruction. the initialization sequence is executed immediately following the internal de- lay. to ensure correct start-up, the user should take care that the vdd supply is stabilized at a suffi- cient level for the chosen frequency (see recom- mended operation) before the reset signal is re- leased. in addition, supply rising must start from 0v. as a consequence, the por does not allow to su- pervise static, slowly rising, or falling, or noisy (presenting oscillation) vdd supplies. an external rc network connected to the r eset pin, or the lvd reset can be used instead to get the best performances. figure 13. reset and interrupt processing int latch cleared nmi mask set reset ( if present ) select nmi mode flags is reset still present? yes put ffeh on address bus from reset locations ffe/fff no fetch instruction load pc va000427 34 19/70 st62t00c/t01c st62t03c/e01c resets (contd) 3.2.3 watchdog reset the mcu provides a watchdog timer function in order to ensure graceful recovery from software upsets. if the watchdog register is not refreshed before an end-of-count condition is reached, the internal reset will be activated. this, amongst oth- er things, resets the watchdog counter. the mcu restarts just as though the reset had been generated by the reset pin, including the built-in stabilisation delay period. 3.2.4 lvd reset the on-chip low voltage detector, selectable as user option, features static reset when supply voltage is below a reference value. thanks to this feature, external reset circuit can be removed while keeping the application safety. this safe reset is effective as well in power-on phase as in power supply drop with different reference val- ues, allowing hysteresis effect. reference value in case of voltage drop has been set lower than the reference value for power-on in order to avoid any parasitic reset when mcu start's running and sinking current on the supply. as long as the supply voltage is below the refer- ence value, there is a internal and static r eset command. the mcu can start only when the sup- ply voltage rises over the reference value. there- fore, only two operating mode exist for the mcu: reset active below the voltage reference, and running mode over the voltage reference as shown on the figure 14 , that represents a power- up, power-down sequence. note : when the reset state is controlled by one of the internal reset sources (low voltage de- tector, watchdog, power on reset), the r eset pin is tied to low logic level. figure 14. lvd reset on power-on and power-down (brown-out) 3.2.5 application notes no external resistor is required between v dd and the reset pin, thanks to the built-in pull-up device. direct external connection of the pin reset to v dd must be avoided in order to ensure safe be- haviour of the internal reset sources (and.wired structure). reset reset vr02106a time v up v dn v dd 35 20/70 st62t00c/t01c st62t03c/e01c resets (contd) 3.2.6 mcu initialization sequence when a reset occurs the stack is reset, the pc is loaded with the address of the reset vector (locat- ed in program rom starting at address 0ffeh). a jump to the beginning of the user program must be coded at this address. following a reset, the in- terrupt flag is automatically set, so that the cpu is in non maskable interrupt mode; this prevents the initialisation routine from being interrupted. the in- itialisation routine should therefore be terminated by a reti instruction, in order to revert to normal mode and enable interrupts. if no pending interrupt is present at the end of the initialisation routine, the mcu will continue by processing the instruction immediately following the reti instruction. if, how- ever, a pending interrupt is present, it will be serv- iced. figure 15. reset and interrupt processing figure 16. reset block diagram reset reset vector jp jp:2 bytes/4 cycles reti reti: 1 byte/2 cycles initialization routine va00181 v dd reset r pu r esd 1) power watchdog reset ck counter reset st6 internal reset f osc reset on reset lvd reset vr02107a and. wired 1) resistive esd protection. value not guaranteed. 36 21/70 st62t00c/t01c st62t03c/e01c resets (contd) table 4. register reset status register address(es) status comment oscillator control register port data registers port direction register port option register interrupt option register timer status/control 0dch 0c0h to 0c1h 0c4h to 0c5h 0cch to 0cdh 0c8h 0d4h 00h f int = f osc ; osg disabled i/o are input with pull-up i/o are input with pull-up i/o are input with pull-up interrupt disabled timer disabled x, y, v, w, register accumulator data ram data rom window register a/d result register 080h to 083h 0ffh 084h to 0bfh 0c9h 0d0h undefined as written if programmed timer counter register timer prescaler register watchdog counter register a/d control register 0d3h 0d2h 0d8h 0d1h ffh 7fh feh 40h max count loaded a/d in standby (when available) 37 22/70 st62t00c/t01c st62t03c/e01c 3.3 digital watchdog the digital watchdog consists of a reloadable downcounter timer which can be used to provide controlled recovery from software upsets. the watchdog circuit generates a reset when the downcounter reaches zero. user software can prevent this reset by reloading the counter, and should therefore be written so that the counter is regularly reloaded while the user program runs correctly. in the event of a software mishap (usual- ly caused by externally generated interference), the user program will no longer behave in its usual fashion and the timer register will thus not be re- loaded periodically. consequently the timer will decrement down to 00h and reset the mcu. in or- der to maximise the effectiveness of the watchdog function, user software must be written with this concept in mind. watchdog behaviour is governed by two options, known as watchdog activation (i.e. hardware or software) and external stop mode control (see table 5 ). in the software option, the watchdog is disa- bled until bit c of the dwdr register has been set. when the watchdog is disabled, low power stop mode is available. once activated, the watchdog cannot be disabled, except by resetting the mcu. in the hardware option, the watchdog is per- manently enabled. since the oscillator will run con- tinuously, low power mode is not available. the stop instruction is interpreted as a wait instruc- tion, and the watchdog continues to countdown. however, when the external stop mode control option has been selected low power consumption may be achieved in stop mode. execution of the stop instruction is then gov- erned by a secondary function associated with the nmi pin. if a stop instruction is encountered when the nmi pin is low, it is interpreted as wait, as described above. if, however, the stop in- struction is encountered when the nmi pin is high, the watchdog counter is frozen and the cpu en- ters stop mode. when the mcu exits stop mode (i.e. when an in- terrupt is generated), the watchdog resumes its activity. table 5. recommended option choices functions required recommended options stop mode & watchdog external stop mode & hardware watchdog stop mode software watchdog watchdog hardware watchdog 38 23/70 st62t00c/t01c st62t03c/e01c digital watchdog (contd) the watchdog is associated with a data space register (digital watchdog register, dwdr, loca- tion 0d8h) which is described in greater detail in section 3.3.1 digital watchdog register (dwdr) . this register is set to 0feh on reset: bit c is cleared to 0, which disables the watchdog; the timer downcounter bits, t0 to t5, and the sr bit are all set to 1, thus selecting the longest watch- dog timer period. this time period can be set to the users requirements by setting the appropriate val- ue for bits t0 to t5 in the dwdr register. the sr bit must be set to 1, since it is this bit which gen- erates the reset signal when it changes to 0; clearing this bit would generate an immediate re- set. it should be noted that the order of the bits in the dwdr register is inverted with respect to the as- sociated bits in the down counter: bit 7 of the dwdr register corresponds, in fact, to t0 and bit 2 to t5. the user should bear in mind the fact that these bits are inverted and shifted with respect to the physical counter bits when writing to this regis- ter. the relationship between the dwdr register bits and the physical implementation of the watch- dog timer downcounter is illustrated in figure 17 . only the 6 most significant bits may be used to de- fine the time period, since it is bit 6 which triggers the reset when it changes to 0. this offers the user a choice of 64 timed periods ranging from 3,072 to 196,608 clock cycles (with an oscillator frequency of 8mhz, this is equivalent to timer peri- ods ranging from 384s to 24.576ms). figure 17. watchdog counter control watchdog control register d0 d1 d3 d4 d5 d6 d7 watchdog counter c sr t5 t4 t3 t2 t1 d2 t0 osc ? 12 reset vr02068a ? 2 8 39 24/70 st62t00c/t01c st62t03c/e01c digital watchdog (contd) 3.3.1 digital watchdog register (dwdr) address: 0d8h read/write reset status: 1111 1110b bit 0 = c : watchdog control bit if the hardware option is selected, this bit is forced high and the user cannot change it (the watchdog is always active). when the software option is se- lected, the watchdog function is activated by set- ting bit c to 1, and cannot then be disabled (save by resetting the mcu). when c is kept low the counter can be used as a 7-bit timer. this bit is cleared to 0 on reset. bit 1 = sr : software reset bit this bit triggers a reset when cleared. when c = 0 (watchdog disabled) it is the msb of the 7-bit timer. this bit is set to 1 on reset. bits 2-7 = t5-t0 : downcounter bits it should be noted that the register bits are re- versed and shifted with respect to the physical counter: bit-7 (t0) is the lsb of the watchdog downcounter and bit-2 (t5) is the msb. these bits are set to 1 on reset. 3.3.2 application notes the watchdog plays an important supporting role in the high noise immunity of st62xx devices, and should be used wherever possible. watchdog re- lated options should be selected on the basis of a trade-off between application security and stop mode availability. when stop mode is not required, hardware acti- vation without external stop mode con- trol should be preferred, as it provides maxi- mum security, especially during power-on. when stop mode is required, hardware activa- tion and external stop mode control should be chosen. nmi should be high by default, to allow stop mode to be entered when the mcu is idle. the nmi pin can be connected to an i/o line (see figure 18 ) to allow its state to be controlled by soft- ware. the i/o line can then be used to keep nmi low while watchdog protection is required, or to avoid noise or key bounce. when no more processing is required, the i/o line is released and the device placed in stop mode for lowest power consumption. when software activation is selected and the watchdog is not activated, the downcounter may be used as a simple 7-bit timer (remember that the bits are in reverse order). the software activation option should be chosen only when the watchdog counter is to be used as a timer. to ensure the watchdog has not been un- expectedly activated, the following instructions should be executed within the first 27 instructions: jrr 0, wd, #+3 ldi wd, 0fdh 70 t0 t1 t2 t3 t4 t5 sr c 40 25/70 st62t00c/t01c st62t03c/e01c digital watchdog (contd) these instructions test the c bit and reset the mcu (i.e. disable the watchdog) if the bit is set (i.e. if the watchdog is active), thus disabling the watchdog. in all modes, a minimum of 28 instructions are ex- ecuted after activation, before the watchdog can generate a reset. consequently, user software should load the watchdog counter within the first 27 instructions following watchdog activation (software mode), or within the first 27 instructions executed following a reset (hardware activation). it should be noted that when the gen bit is low (in- terrupts disabled), the nmi interrupt is active but cannot cause a wake up from stop/wait modes. figure 18. a typical circuit making use of the exernal stop mode control feature figure 19. digital watchdog block diagram nmi switch i/o vr02002 rsff 8 data bus va00010 -2 -12 oscillator reset write reset db0 r s q db1.7 set load 7 8 -2 set clock 41 26/70 st62t00c/t01c st62t03c/e01c 3.4 interrupts the cpu can manage four maskable interrupt sources, in addition to a non maskable interrupt source (top priority interrupt). each source is asso- ciated with a specific interrupt vector which con- tains a jump instruction to the associated interrupt service routine. these vectors are located in pro- gram space (see table 6 ). when an interrupt source generates an interrupt request, and interrupt processing is enabled, the pc register is loaded with the address of the inter- rupt vector (i.e. of the jump instruction), which then causes a jump to the relevant interrupt serv- ice routine, thus servicing the interrupt. interrupt sources are linked to events either on ex- ternal pins, or on chip peripherals. several events can be ored on the same interrupt source, and relevant flags are available to determine which event triggered the interrupt. the non maskable interrupt request has the high- est priority and can interrupt any interrupt routine at any time; the other four interrupts cannot inter- rupt each other. if more than one interrupt request is pending, these are processed by the processor core according to their priority level: source #1 has the higher priority while source #4 the lower. the priority of each interrupt source is fixed. table 6. interrupt vector map 3.4.1 interrupt request all interrupt sources but the non maskable inter- rupt source can be disabled by setting accordingly the gen bit of the interrupt option register (ior). this gen bit also defines if an interrupt source, in- cluding the non maskable interrupt source, can re- start the mcu from stop/wait modes. interrupt request from the non maskable interrupt source #0 is latched by a flip flop which is automat- ically reset by the core at the beginning of the non- maskable interrupt service routine. interrupt request from source #1 can be config- ured either as edge or level sensitive by setting ac- cordingly the les bit of the interrupt option regis- ter (ior). interrupt request from source #2 are always edge sensitive. the edge polarity can be configured by setting accordingly the esb bit of the interrupt op- tion register (ior). interrupt request from sources #3 & #4 are level sensitive. in edge sensitive mode, a latch is set when a edge occurs on the interrupt source line and is cleared when the associated interrupt routine is started. so, the occurrence of an interrupt can be stored, until completion of the running interrupt routine be- fore being processed. if several interrupt requests occurs before completion of the running interrupt routine, only the first request is stored. storage of interrupt requests is not available in lev- el sensitive mode. to be taken into account, the low level must be present on the interrupt pin when the mcu samples the line after instruction execu- tion. at the end of every instruction, the mcu tests the interrupt lines: if there is an interrupt request the next instruction is not executed and the appropri- ate interrupt service routine is executed instead. table 7. interrupt option register description interrupt source priority vector address interrupt source #0 1 (ffch-ffdh) interrupt source #1 2 (ff6h-ff7h) interrupt source #2 3 (ff4h-ff5h) interrupt source #3 4 (ff2h-ff3h) interrupt source #4 5 (ff0h-ff1h) gen set enable all interrupts cleared disable all interrupts esb set rising edge mode on inter- rupt source #2 cleared falling edge mode on inter- rupt source #2 les set level-sensitive mode on in- terrupt source #1 cleared falling edge mode on inter- rupt source #1 others not used 42 27/70 st62t00c/t01c st62t03c/e01c interrupts (contd) 3.4.2 interrupt procedure the interrupt procedure is very similar to a call pro- cedure, indeed the user can consider the interrupt as an asynchronous call procedure. as this is an asynchronous event, the user cannot know the context and the time at which it occurred. as a re- sult, the user should save all data space registers which may be used within the interrupt routines. there are separate sets of processor flags for nor- mal, interrupt and non-maskable interrupt modes, which are automatically switched and so do not need to be saved. the following list summarizes the interrupt proce- dure: mcu C the interrupt is detected. C the c and z flags are replaced by the interrupt flags (or by the nmi flags). C the pc contents are stored in the first level of the stack. C the normal interrupt lines are inhibited (nmi still active). C the first internal latch is cleared. C the associated interrupt vector is loaded in the pc. warning: in some circumstances, when a maskable interrupt occurs while the st6 core is in normal mode and especially during the execu- tion of an "ldi ior, 00h" instruction (disabling all maskable interrupts): if the interrupt arrives during the first 3 cycles of the "ldi" instruction (which is a 4-cycle instruction) the core will switch to interrupt mode but the flags cn and zn will not switch to the interrupt pair ci and zi. user C user selected registers are saved within the in- terrupt service routine (normally on a software stack). C the source of the interrupt is found by polling the interrupt flags (if more than one source is associ- ated with the same vector). C the interrupt is serviced. C return from interrupt (reti) mcu C automatically the mcu switches back to the nor- mal flag set (or the interrupt flag set) and pops the previous pc value from the stack. the interrupt routine usually begins by the identify- ing the device which generated the interrupt re- quest (by polling). the user should save the regis- ters which are used within the interrupt routine in a software stack. after the reti instruction is exe- cuted, the mcu returns to the main routine. figure 20. interrupt processing flow chart instruction fetch instruction execute instruction was the instruction a reti ? ? clear interrupt mask select program flags "pop" the stacked pc ? check if there is an interrupt request and interrupt mask select internal mode flag push the pc into the stack load pc from interrupt vector (ffc/ffd) set interrupt mask no no yes is the c ore already in normal mode? va000014 yes no yes 43 28/70 st62t00c/t01c st62t03c/e01c interrupts (contd) 3.4.3 interrupt option register (ior) the interrupt option register (ior) is used to en- able/disable the individual interrupt sources and to select the operating mode of the external interrupt inputs. this register is write-only and cannot be accessed by single-bit operations. address: 0c8h write only reset status: 00h bit 7, bits 3-0 = unused . bit 6 = les : level/edge selection bit . when this bit is set to one, the interrupt source #1 is level sensitive. when cleared to zero the edge sensitive mode for interrupt request is selected. bit 5 = esb : edge selection bit . the bit esb selects the polarity of the interrupt source #2. bit 4 = gen : global enable interrupt . when this bit is set to one, all interrupts are enabled. when this bit is cleared to zero all the interrupts (excluding nmi) are disabled. when the gen bit is low, the nmi interrupt is ac- tive but cannot cause a wake up from stop/wait modes. this register is cleared on reset. 3.4.4 interrupt sources interrupt sources available on the st62e01c/ t01c are summarized in the table 8 with associ- ated mask bit to enable/disable the interrupt re- quest. table 8. interrupt requests and mask bits *except st62t03c 70 - les esb gen - - - - peripheral register address register mask bit masked interrupt source interrupt vector general ior c8h gen all interrupts, excluding nm i timer tscr d4h eti tmz: timer overflow vector 3 a/d converter(*) adcr d1h eai eoc: end of conversion vector 4 port pan orpa-drpa c4h-cch orpan-drpan pan pin vector 1 port pbn orpb-drpb c5h-cdh orpbn-drpbn pbn pin vector 2 44 29/70 st62t00c/t01c st62t03c/e01c interrupts (contd) figure 21. interrupt block diagram nmi v dd ff clk q clr int #0 - nmi (ffc,d) i 0 start restart from stop/wait int #1 (ff6,7) ff clk q clr pbe 0 mux 1 port a port b bits int #2 (ff4,5) int #3 (ff2,3) tmz eti timer ff clk q clr ior reg. c8h, bit 5 i 1 start i 2 start ior reg. c8h, bit 6 pbe pbe v dd from register single bit enable port a,b pbe int #4 (ff0,1) eai eoc adc(*) gen va0426t (*)except on st62t03c 45 30/70 st62t00c/t01c st62t03c/e01c 3.5 power saving modes the wait and stop modes have been imple- mented in the st62xx family of mcus in order to reduce the products electrical consumption during idle periods. these two power saving modes are described in the following paragraphs. in addition, the low frequency auxiliary oscillator (lfao) can be used instead of the main oscillator to reduce power consumption in run and wait modes. 3.5.1 wait mode the mcu goes into wait mode as soon as the wait instruction is executed. the microcontroller can be considered as being in a software frozen state where the core stops processing the pro- gram instructions, the ram contents and peripher- al registers are preserved as long as the power supply voltage is higher than the ram retention voltage. in this mode the peripherals are still ac- tive. wait mode can be used when the user wants to reduce the mcu power consumption during idle periods, while not losing track of time or the capa- bility of monitoring external events. the active os- cillator (main oscillator or lfao) is not stopped in order to provide a clock signal to the peripherals. timer counting may be enabled as well as the timer interrupt, before entering the wait mode: this allows the wait mode to be exited when a timer interrupt occurs. the same applies to other peripherals which use the clock signal. if the power consumption has to be further re- duced, the low frequency auxiliary oscillator (lfao) can be used in place of the main oscillator, if its operating frequency is lower. if required, the lfao must be switched on before entering the wait mode. if the wait mode is exited due to a reset (either by activating the external pin or generated by the watchdog), the mcu enters a normal reset proce- dure. if an interrupt is generated during wait mode, the mcus behaviour depends on the state of the processor core prior to the wait instruction, but also on the kind of interrupt request which is generated. this is described in the following para- graphs. the processor core does not generate a delay following the occurrence of the interrupt, be- cause the oscillator clock is still available and no stabilisation period is necessary. 3.5.2 stop mode if the watchdog is disabled, stop mode is availa- ble. when in stop mode, the mcu is placed in the lowest power consumption mode. in this oper- ating mode, the microcontroller can be considered as being frozen, no instruction is executed, the oscillator is stopped, the ram contents and pe- ripheral registers are preserved as long as the power supply voltage is higher than the ram re- tention voltage, and the st62xx core waits for the occurrence of an external interrupt request or a reset to exit the stop state. if the stop state is exited due to a reset (by acti- vating the external pin) the mcu will enter a nor- mal reset procedure. behaviour in response to in- terrupts depends on the state of the processor core prior to issuing the stop instruction, and also on the kind of interrupt request that is gener- ated. this case will be described in the following para- graphs. the processor core generates a delay af- ter occurrence of the interrupt request, in order to wait for complete stabilisation of the oscillator, be- fore executing the first instruction. 46 31/70 st62t00c/t01c st62t03c/e01c power saving mode (contd) 3.5.3 exit from wait and stop modes the following paragraphs describe how the mcu exits from wait and stop modes, when an inter- rupt occurs (not a reset). it should be noted that the restart sequence depends on the original state of the mcu (normal, interrupt or non-maskable in- terrupt mode) prior to entering wait or stop mode, as well as on the interrupt type. interrupts do not affect the oscillator selection, consequently, when the lfao is used, the user program must manage oscillator selection as soon as normal run mode is resumed. 3.5.3.1 normal mode if the mcu was in the main routine when the wait or stop instruction was executed, exit from stop or wait mode will occur as soon as an interrupt oc- curs; the related interrupt routine is executed and, on completion, the instruction which follows the stop or wait instruction is then executed, pro- viding no other interrupts are pending. 3.5.3.2 non maskable interrupt mode if the stop or wait instruction has been execut- ed during execution of the non-maskable interrupt routine, the mcu exits from the stop or wait mode as soon as an interrupt occurs: the instruction which follows the stop or wait instruction is ex- ecuted, and the mcu remains in non-maskable in- terrupt mode, even if another interrupt has been generated. 3.5.3.3 normal interrupt mode if the mcu was in interrupt mode before the stop or wait instruction was executed, it exits from stop or wait mode as soon as an interrupt oc- curs. nevertheless, two cases must be consid- ered: C if the interrupt is a normal one, the interrupt rou- tine in which the wait or stop mode was en- tered will be completed, starting with the execution of the instruction which follows the stop or the wait instruction, and the mcu is still in the interrupt mode. at the end of this rou- tine pending interrupts will be serviced in accord- ance with their priority. C in the event of a non-maskable interrupt, the non-maskable interrupt service routine is proc- essed first, then the routine in which the wait or stop mode was entered will be completed by executing the instruction following the stop or wait instruction. the mcu remains in normal in- terrupt mode. notes: to achieve the lowest power consumption during run or wait modes, the user program must take care of: C configuring unused i/os as inputs without pull-up (these should be externally tied to well defined logic levels); C placing all peripherals in their power down modes before entering stop mode; C selecting the low frequency auxiliary oscillator (provided this runs at a lower frequency than the main oscillator). when the hardware activated watchdog is select- ed, or when the software watchdog is enabled, the stop instruction is disabled and a wait instruc- tion will be executed in its place. if all interrupt sources are disabled (gen low), the mcu can only be restarted by a reset. although setting gen low does not mask the nmi as an in- terrupt, it will stop it generating a wake-up signal. the wait and stop instructions are not execut- ed if an enabled interrupt request is pending. 47 32/70 st62t00c/t01c st62t03c/e01c 4 on-chip peripherals 4.1 i/o ports the mcu features input/output lines which may be individually programmed as any of the following input or output configurations: C input without pull-up or interrupt C input with pull-up and interrupt C input with pull-up, but without interrupt C analog input C push-pull output C open drain output the lines are organised as bytewise ports. each port is associated with 3 registers in data space. each bit of these registers is associated with a particular line (for instance, bits 0 of port a data, direction and option registers are associat- ed with the pa0 line of port a). the data registers (drx), are used to read the voltage level values of the lines which have been configured as inputs, or to write the logic value of the signal to be output on the lines configured as outputs. the port data registers can be read to get the effective logic levels of the pins, but they can be also written by user software, in conjunction with the related option registers, to select the dif- ferent input mode options. single-bit operations on i/o registers are possible but care is necessary because reading in input mode is done from i/o pins while writing will direct- ly affect the port data register causing an unde- sired change of the input configuration. the data direction registers (ddrx) allow the data direction (input or output) of each pin to be set. the option registers (orx) are used to select the different port options available both in input and in output mode. all i/o registers can be read or written to just as any other ram location in data space, so no extra ram cells are needed for port data storage and manipulation. during mcu initialization, all i/o reg- isters are cleared and the input mode with pull-ups and no interrupt generation is selected for all the pins, thus avoiding pin conflicts. figure 22. i/o port block diagram v dd reset s in controls s out shift register data data direction register register option register input/output to interrupt v dd to adc va00413 48 33/70 st62t00c/t01c st62t03c/e01c i/o ports (contd) 4.1.1 operating modes each pin may be individually programmed as input or output with various configurations. this is achieved by writing the relevant bit in the data (dr), data direction (ddr) and option reg- isters (or). table 9 illustrates the various port configurations which can be selected by user soft- ware. 4.1.1.1 input options pull-up, high impedance option. all input lines can be individually programmed with or without an internal pull-up by programming the or and dr registers accordingly. if the pull-up option is not selected, the input pin will be in the high-imped- ance state. 4.1.1.2 interrupt options all input lines can be individually connected by software to the interrupt system by programming the or and dr registers accordingly. the inter- rupt trigger modes (falling edge, rising edge and low level) can be configured by software as de- scribed in the interrupt chapter for each port. 4.1.1.3 analog input options some pins can be configured as analog inputs by programming the or and dr registers according- ly. these analog inputs are connected to the on- chip 8-bit analog to digital converter. only one pin should be programmed as an analog input at any time, since by selecting more than one input simultaneously their pins will be effectively short- ed. table 9. i/o port option selection note: x = dont care ddr or dr mode option 0 0 0 input with pull-up, no interrupt 0 0 1 input no pull-up, no interrupt 0 1 0 input with pull-up and with interrupt 0 1 1 input analog input (when available) 1 0 x output open-drain output (20ma sink when available) 1 1 x output push-pull output (20ma sink when available) 49 34/70 st62t00c/t01c st62t03c/e01c i/o ports (contd) 4.1.2 safe i/o state switching sequence switching the i/o ports from one state to another should be done in a sequence which ensures that no unwanted side effects can occur. the recom- mended safe transitions are illustrated in figure 23 . all other transitions are potentially risky and should be avoided when changing the i/o operat- ing mode, as it is most likely that undesirable side- effects will be experienced, such as spurious inter- rupt generation or two pins shorted together by the analog multiplexer. single bit instructions (set, res, inc and dec) should be used with great caution on ports data registers, since these instructions make an implicit read and write back of the entire register. in port input mode, however, the data register reads from the input pins directly, and not from the data regis- ter latches. since data register information in input mode is used to set the characteristics of the input pin (interrupt, pull-up, analog input), these may be unintentionally reprogrammed depending on the state of the input pins. as a general rule, it is better to limit the use of single bit instructions on data registers to when the whole (8-bit) port is in output mode. in the case of inputs or of mixed inputs and outputs, it is advisable to keep a copy of the data register in ram. single bit instructions may then be used on the ram copy, after which the whole copy register can be written to the port data regis- ter: set bit, datacopy ld a, datacopy ld dra, a warning: care must also be taken to not use in- structions that act on a whole port register (inc, dec, or read operations) when all 8 bits are not available on the device. unavailable bits must be masked by software (and instruction). the wait and stop instructions allow the st62xx to be used in situations where low power consumption is needed. the lowest power con- sumption is achieved by configuring i/os in input mode with well-defined logic levels. the user must take care not to switch outputs with heavy loads during the conversion of one of the analog inputs in order to avoid any disturbance to the conversion. figure 23. diagram showing safe i/o state transitions note *. xxx = ddr, or, dr bits respectively interrupt pull-up output open drain output push-pull input pull-up (reset state) input analog output open drain output push-pull input 010* 000 100 110 011 001 101 111 50 35/70 st62t00c/t01c st62t03c/e01c i/o ports (contd) 4.1.3 i/o port option registers ora/b (cch pa, cdh pb) read/write bit 7-0 = px7 - px0 : port a and b option register bits. 4.1.4 i/o port data direction registers ddra/b (c4h pa, c5h pb) read/write bit 7-0 = px7 - px0: port a and b data direction registers bits. 4.1.5 i/o port data registers dra/b (c0h pa, c1h pb) read/write bit 7-0 = px7 - px0 : port a and b data registers bits. note: x = dont care 70 px7 px6 px5 px4 px3 px2 px1 px0 70 px7 px6 px5 px4 px3 px2 px1 px0 70 px7 px6 px5 px4 px3 px2 px1 px0 51 36/70 st62t00c/t01c st62t03c/e01c i/o ports (contd) table 10. i/o port option selections note 1 . provided the correct configuration has been selected. mode available on (1) schematic input pa1-pa3 pb0,pb1,pb3,pb5-pb7 input with pull up pa1-pa3 pb0,pb1,pb3,pb5-pb7 input with pull up with interrupt pa1-pa3 pb0,pb1,pb3,pb5-pb7 analog input pb3,pb5-pb7 (except st62t03c) open drain output 5ma open drain output 20ma pb0,pb1,pb3,pb5-pb7 pa1-pa3 push-pull output 5ma push-pull output 20ma pb0,pb1,pb3,pb5-pb7 pa1-pa3 data in interrupt data in interrupt data in interrupt data out adc data out 52 37/70 st62t00c/t01c st62t03c/e01c 4.2 timer the mcu features an on-chip timer peripheral, consisting of an 8-bit counter with a 7-bit program- mable prescaler, giving a maximum count of 2 15 . figure 24 shows the timer block diagram. the content of the 8-bit counter can be read/written in the timer/counter register, tcr, which can be ad- dressed in data space as a ram location at ad- dress 0d3h. the state of the 7-bit prescaler can be read in the psc register at address 0d2h. the control logic device is managed in the tscr reg- ister as described in the following paragraphs. the 8-bit counter is decrement by the output (ris- ing edge) coming from the 7-bit prescaler and can be loaded and read under program control. when it decrements to zero then the tmz (timer zero)bit in the tscr is set. if the eti (enable timer inter- rupt) bit in the tscr is also set, an interrupt re- quest is generated. the timer interrupt can be used to exit the mcu from wait mode. the prescaler input is the internal frequency (f int ) divided by 12. the prescaler decrements on the rising edge. depending on the division factor pro- grammed by ps2, ps1 and ps0 bits in the tscr (see figure 11 ), the clock input of the timer/coun- ter register is multiplexed to different sources. for division factor 1, the clock input of the prescaler is also that of timer/counter; for factor 2, bit 0 of the prescaler register is connected to the clock input of tcr. this bit changes its state at half the frequen- cy of the prescaler input clock. for factor 4, bit 1 of the psc is connected to the clock input of tcr, and so forth. the prescaler initialize bit, psi, in the tscr register must be set to allow the prescaler (and hence the counter) to start. if it is cleared, all the prescaler bits are set and the counter is inhib- ited from counting. the prescaler can be loaded with any value between 0 and 7fh, if bit psi is set. the prescaler tap is selected by means of the ps2/ps1/ps0 bits in the control register. figure 25 illustrates the timers working principle. figure 24. timer block diagram data bus 8-bit counter status/control register interrupt line vr02070a 3 8 8 8 6 5 4 3 2 1 0 select 1 of 7 12 b7 b6 b5 b4 b3 b2 b1 b0 tmz eti d5 d4 psi ps2 ps1 ps0 f int psc 53 38/70 st62t00c/t01c st62t03c/e01c timer (contd) 4.2.1 timer operation the timer prescaler is clocked by the prescaler clock input (f int 12). the user can select the desired prescaler division ratio through the ps2, ps1, ps0 bits. when the tcr count reaches 0, it sets the tmz bit in the tscr. the tmz bit can be tested under program control to perform a timer function whenever it goes high. 4.2.2 timer interrupt when the counter register decrements to zero with the eti (enable timer interrupt) bit set to one, an interrupt request associated with interrupt vector #3 is generated. when the counter decrements to zero, the tmz bit in the tscr register is set to one. 4.2.3 application notes tmz is set when the counter reaches zero; howev- er, it may also be set by writing 00h in the tcr register or by setting bit 7 of the tscr register. the tmz bit must be cleared by user software when servicing the timer interrupt to avoid unde- sired interrupts when leaving the interrupt service routine. after reset, the 8-bit counter register is loaded with 0ffh, while the 7-bit prescaler is load- ed with 07fh, and the tscr register is cleared. this means that the timer is stopped (psi=0) and the timer interrupt is disabled. figure 25. timer working principle bit0 bit1 bit2 bit3 bit6 bit5 bit4 clock 7-bit prescaler 8-1 multiplexer 8-bit counter bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 1 0 2 34 5 67 ps0 ps1 ps2 va00186 54 39/70 st62t00c/t01c st62t03c/e01c timer (contd) a write to the tcr register will predominate over the 8-bit counter decrement to 00h function, i.e. if a write and a tcr register decrement to 00h occur simultaneously, the write will take precedence, and the tmz bit is not set until the 8-bit counter reaches 00h again. the values of the tcr and the psc registers can be read accurately at any time. 4.2.4 timer registers timer status control register (tscr) address: 0d4h read/write bit 7 = tmz : timer zero bit a low-to-high transition indicates that the timer count register has decrement to zero. this bit must be cleared by user software before starting a new count. bit 6 = eti : enable timer interrup when set, enables the timer interrupt request (vector #3). if eti=0 the timer interrupt is disabled. if eti=1 and tmz=1 an interrupt request is gener- ated. bit 5 = d5 : reserved must be set to 1. bit 4 = d4 do not care. bit 3 = psi : prescaler initialize bit used to initialize the prescaler and inhibit its count- ing. when psi=0 the prescaler is set to 7fh and the counter is inhibited. when psi=1 the prescal- er is enabled to count downwards. as long as psi=0 both counter and prescaler are not run- ning. bit 2, 1, 0 = ps2, ps1, ps0 : prescaler mux. se- lect. these bits select the division ratio of the pres- caler register. table 11. prescaler division factors timer counter register tcr address: 0d3h read/write bit 7-0 = d7-d0 : counter bits. prescaler register psc address: 0d2h read/write bit 7 = d7 : always read as "0". bit 6-0 = d6-d0 : prescaler bits. 70 tmz eti d5 d4 psi ps2 ps1 ps0 ps2 ps1 ps0 divided by 0 0 0 1 0 0 1 2 0 1 0 4 0118 10016 10132 11064 111128 70 d7 d6 d5 d4 d3 d2 d1 d0 70 d7 d6 d5 d4 d3 d2 d1 d0 55 40/70 st62t00c/t01c st62t03c/e01c 4.3 a/d converter (adc) the a/d converter peripheral is an 8-bit analog to digital converter with analog inputs as alternate i/o functions (the number of which is device depend- ent), offering 8-bit resolution with a typical conver- sion time of 70us (at an oscillator clock frequency of 8mhz). the adc converts the input voltage by a process of successive approximations, using a clock fre- quency derived from the oscillator with a division factor of twelve. with an oscillator clock frequency less than 1.2mhz, conversion accuracy is de- creased. selection of the input pin is done by configuring the related i/o line as an analog input via the op- tion and data registers (refer to i/o ports descrip- tion for additional information). only one i/o line must be configured as an analog input at any time. the user must avoid any situation in which more than one i/o pin is selected as an analog input si- multaneously, to avoid device malfunction. the adc uses two registers in the data space: the adc data conversion register, adr, which stores the conversion result, and the adc control regis- ter, adcr, used to program the adc functions. a conversion is started by writing a 1 to the start bit (sta) in the adc control register. this auto- matically clears (resets to 0) the end of conver- sion bit (eoc). when a conversion is complete, the eoc bit is automatically set to 1, in order to flag that conversion is complete and that the data in the adc data conversion register is valid. each conversion has to be separately initiated by writing to the sta bit. the sta bit is continuously scanned so that, if the user sets it to 1 while a previous conversion is in progress, a new conversion is started before com- pleting the previous one. the start bit (sta) is a write only bit, any attempt to read it will show a log- ical 0. the a/d converter features a maskable interrupt associated with the end of conversion. this inter- rupt is associated with interrupt vector #4 and oc- curs when the eoc bit is set (i.e. when a conver- sion is completed). the interrupt is masked using the eai (interrupt mask) bit in the control register. the power consumption of the device can be re- duced by turning off the adc peripheral. this is done by setting the pds bit in the adc control reg- ister to 0. if pds=1, the a/d is powered and en- abled for conversion. this bit must be set at least one instruction before the beginning of the conver- sion to allow stabilisation of the a/d converter. this action is also needed before entering wait mode, since the a/d comparator is not automati- cally disabled in wait mode. during reset, any conversion in progress is stopped, the control register is reset to 40h and the adc interrupt is masked (eai=0). figure 26. adc block diagram 4.3.1 application notes the a/d converter does not feature a sample and hold circuit. the analog voltage to be measured should therefore be stable during the entire con- version cycle. voltage variation should not exceed 1/2 lsb for the optimum conversion accuracy. a low pass filter may be used at the analog input pins to reduce input voltage variation during con- version. when selected as an analog channel, the input pin is internally connected to a capacitor c ad of typi- cally 12pf. for maximum accuracy, this capacitor must be fully charged at the beginning of conver- sion. in the worst case, conversion starts one in- struction (6.5 s) after the channel has been se- lected. in worst case conditions, the impedance, asi, of the analog voltage source is calculated us- ing the following formula: 6.5s = 9 x c ad x asi (capacitor charged to over 99.9%), i.e. 30 k w in- cluding a 50% guardband. asi can be higher if c ad has been charged for a longer period by adding in- structions before the start of conversion (adding more than 26 cpu cycles is pointless). control register converter va00418 result register reset interrupt clock av av dd ain 8 core control signals ss 8 core 56 41/70 st62t00c/t01c st62t03c/e01c a/d converter (contd) since the adc is on the same chip as the micro- processor, the user should not switch heavily load- ed output signals during conversion, if high preci- sion is required. such switching will affect the sup- ply voltages used as analog references. the accuracy of the conversion depends on the quality of the power supplies (v dd and v ss ). the user must take special care to ensure a well regu- lated reference voltage is present on the v dd and v ss pins (power supply voltage variations must be less than 5v/ms). this implies, in particular, that a suitable decoupling capacitor is used at the v dd pin. the converter resolution is given by:: the input voltage (ain) which is to be converted must be constant for 1s before conversion and remain constant during conversion. conversion resolution can be improved if the pow- er supply voltage (v dd ) to the microcontroller is lowered. in order to optimise conversion resolution, the user can configure the microcontroller in wait mode, because this mode minimises noise disturbances and power supply variations due to output switch- ing. nevertheless, the wait instruction should be executed as soon as possible after the beginning of the conversion, because execution of the wait instruction may cause a small variation of the v dd voltage. the negative effect of this variation is min- imized at the beginning of the conversion when the converter is less sensitive, rather than at the end of conversion, when the less significant bits are determined. the best configuration, from an accuracy stand- point, is wait mode with the timer stopped. in- deed, only the adc peripheral and the oscillator are then still working. the mcu must be woken up from wait mode by the adc interrupt at the end of the conversion. it should be noted that waking up the microcontroller could also be done using the timer interrupt, but in this case the timer will be working and the resulting noise could affect conversion accuracy. a/d converter control register (adcr) address: 0d1h read/write bit 7 = eai : enable a/d interrupt. if this bit is set to 1 the a/d interrupt is enabled, when eai=0 the interrupt is disabled. bit 6 = eoc : end of conversion. read only . this read only bit indicates when a conversion has been completed. this bit is automatically reset to 0 when the sta bit is written. if the user is using the interrupt option then this bit can be used as an interrupt pending bit. data in the data conversion register are valid only when this bit is set to 1. bit 5 = sta : start of conversion. write only . writ- ing a 1 to this bit will start a conversion on the se- lected channel and automatically reset to 0 the eoc bit. if the bit is set again when a conversion is in progress, the present conversion is stopped and a new one will take place. this bit is write only, any attempt to read it will show a logical zero. bit 4 = pds : power down selection. this bit acti- vates the a/d converter if set to 1. writing a 0 to this bit will put the adc in power down mode (idle mode). bit 3-0 = d3-d0. not used a/d converter data register (adr) address: 0d0h read only bit 7-0 = d7-d0 : 8 bit a/d conversion result. v dd v ss C 256 --------------------------- - 70 eai eoc sta pds d3 d2 d1 d0 70 d7 d6 d5 d4 d3 d2 d1 d0 57 42/70 st62t00c/t01c st62t03c/e01c 5 software 5.1 st6 architecture the st6 software has been designed to fully use the hardware in the most efficient way possible while keeping byte usage to a minimum; in short, to provide byte efficient programming capability. the st6 core has the ability to set or clear any register or ram location bit of the data space with a single instruction. furthermore, the program may branch to a selected address depending on the status of any bit of the data space. the carry bit is stored with the value of the bit when the set or res instruction is processed. 5.2 addressing modes the st6 core offers nine addressing modes, which are described in the following paragraphs. three different address spaces are available: pro- gram space, data space, and stack space. pro- gram space contains the instructions which are to be executed, plus the data for immediate mode in- structions. data space contains the accumulator, the x,y,v and w registers, peripheral and input/ output registers, the ram locations and data rom locations (for storage of tables and con- stants). stack space contains six 12-bit ram cells used to stack the return addresses for subroutines and interrupts. immediate . in the immediate addressing mode, the operand of the instruction follows the opcode location. as the operand is a rom byte, the imme- diate addressing mode is used to access con- stants which do not change during program execu- tion (e.g., a constant used to initialize a loop coun- ter). direct . in the direct addressing mode, the address of the byte which is processed by the instruction is stored in the location which follows the opcode. di- rect addressing allows the user to directly address the 256 bytes in data space memory with a single two-byte instruction. short direct . the core can address the four ram registers x,y,v,w (locations 80h, 81h, 82h, 83h) in the short-direct addressing mode. in this case, the instruction is only one byte and the selection of the location to be processed is contained in the op- code. short direct addressing is a subset of the di- rect addressing mode. (note that 80h and 81h are also indirect registers). extended . in the extended addressing mode, the 12-bit address needed to define the instruction is obtained by concatenating the four less significant bits of the opcode with the byte following the op- code. the instructions (jp, call) which use the extended addressing mode are able to branch to any address of the 4k bytes program space. an extended addressing mode instruction is two- byte long. program counter relative . the relative address- ing mode is only used in conditional branch in- structions. the instruction is used to perform a test and, if the condition is true, a branch with a span of -15 to +16 locations around the address of the rel- ative instruction. if the condition is not true, the in- struction which follows the relative instruction is executed. the relative addressing mode instruc- tion is one-byte long. the opcode is obtained in adding the three most significant bits which char- acterize the kind of the test, one bit which deter- mines whether the branch is a forward (when it is 0) or backward (when it is 1) branch and the four less significant bits which give the span of the branch (0h to fh) which must be added or sub- tracted to the address of the relative instruction to obtain the address of the branch. bit direct . in the bit direct addressing mode, the bit to be set or cleared is part of the opcode, and the byte following the opcode points to the ad- dress of the byte in which the specified bit must be set or cleared. thus, any bit in the 256 locations of data space memory can be set or cleared. bit test & branch . the bit test and branch ad- dressing mode is a combination of direct address- ing and relative addressing. the bit test and branch instruction is three-byte long. the bit iden- tification and the tested condition are included in the opcode byte. the address of the byte to be tested follows immediately the opcode in the pro- gram space. the third byte is the jump displace- ment, which is in the range of -127 to +128. this displacement can be determined using a label, which is converted by the assembler. indirect . in the indirect addressing mode, the byte processed by the register-indirect instruction is at the address pointed by the content of one of the in- direct registers, x or y (80h,81h). the indirect reg- ister is selected by the bit 4 of the opcode. a regis- ter indirect instruction is one byte long. inherent . in the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. these instructions are one byte long. 58 43/70 st62t00c/t01c st62t03c/e01c 5.3 instruction set the st6 core offers a set of 40 basic instructions which, when combined with nine addressing modes, yield 244 usable opcodes. they can be di- vided into six different types: load/store, arithme- tic/logic, conditional branch, control instructions, jump/call, and bit manipulation. the following par- agraphs describe the different types. all the instructions belonging to a given type are presented in individual tables. load & store . these instructions use one, two or three bytes in relation with the addressing mode. one operand is the accumulator for load and the other operand is obtained from data memory using one of the addressing modes. for load immediate one operand can be any of the 256 data space bytes while the other is always immediate data. table 12. load & store instructions notes: x,y. indirect register pointers, v & w short direct registers # . immediate data (stored in rom memory) rr. data space register d . affected * . not affected instruction addressing mode bytes cycles flags zc ld a, x short direct 1 4 d * ld a, y short direct 1 4 d * ld a, v short direct 1 4 d * ld a, w short direct 1 4 d * ld x, a short direct 1 4 d * ld y, a short direct 1 4 d * ld v, a short direct 1 4 d * ld w, a short direct 1 4 d * ld a, rr direct 2 4 d * ld rr, a direct 2 4 d * ld a, (x) indirect 1 4 d * ld a, (y) indirect 1 4 d * ld (x), a indirect 1 4 d * ld (y), a indirect 1 4 d * ldi a, #n immediate 2 4 d * ldi rr, #n immediate 3 4 * * 59 44/70 st62t00c/t01c st62t03c/e01c instruction set (contd) arithmetic and logic . these instructions are used to perform the arithmetic calculations and logic operations. in and, add, cp, sub instruc- tions one operand is always the accumulator while the other can be either a data space memory con- tent or an immediate value in relation with the ad- dressing mode. in clr, dec, inc instructions the operand can be any of the 256 data space ad- dresses. in com, rlc, sla the operand is always the accumulator. table 13. arithmetic & logic instructions notes: x,y.indirect register pointers, v & w short direct registersd. affected # . immediate data (stored in rom memory)* . not affected rr. data space register instruction addressing mode bytes cycles flags zc add a, (x) indirect 1 4 dd add a, (y) indirect 1 4 dd add a, rr direct 2 4 dd addi a, #n immediate 2 4 dd and a, (x) indirect 1 4 dd and a, (y) indirect 1 4 dd and a, rr direct 2 4 dd andi a, #n immediate 2 4 dd clr a short direct 2 4 dd clr r direct 3 4 * * com a inherent 1 4 dd cp a, (x) indirect 1 4 dd cp a, (y) indirect 1 4 dd cp a, rr direct 2 4 dd cpi a, #n immediate 2 4 dd dec x short direct 1 4 d * dec y short direct 1 4 d * dec v short direct 1 4 d * dec w short direct 1 4 d * dec a direct 2 4 d * dec rr direct 2 4 d * dec (x) indirect 1 4 d * dec (y) indirect 1 4 d * inc x short direct 1 4 d * inc y short direct 1 4 d * inc v short direct 1 4 d * inc w short direct 1 4 d * inc a direct 2 4 d * inc rr direct 2 4 d * inc (x) indirect 1 4 d * inc (y) indirect 1 4 d * rlc a inherent 1 4 dd sla a inherent 2 4 dd sub a, (x) indirect 1 4 dd sub a, (y) indirect 1 4 dd sub a, rr direct 2 4 dd subi a, #n immediate 2 4 dd 60 45/70 st62t00c/t01c st62t03c/e01c instruction set (contd) conditional branch . the branch instructions achieve a branch in the program when the select- ed condition is met. bit manipulation instructions . these instruc- tions can handle any bit in data space memory. one group either sets or clears. the other group (see conditional branch) performs the bit test branch operations. control instructions . the control instructions control the mcu operations during program exe- cution. jump and call. these two instructions are used to perform long (12-bit) jumps or subroutines call inside the whole program space. table 14. conditional branch instructions notes : b. 3-bit address rr. data space register e. 5 bit signed displacement in the range -15 to +16 46/70 st62t00c/t01c st62t03c/e01c opcode map summary. the following table contains an opcode map for the instructions used by the st6 low 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 low hi hi 0 0000 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 ld 0 0000 e abc e b0,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 1 0001 2 jrnz4 call2 jrnc5 jrs2 jrz4 inc2 jrc4 ldi 1 0001 e abc e b0,rr,ee e x e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm 2 0010 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 cp 2 0010 e abc e b4,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 3 0011 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 ld 2 jrc 4 cpi 3 0011 e abc e b4,rr,ee e a,x e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm 4 0100 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 add 4 0100 e abc e b2,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 5 0101 2 jrnz4 call2 jrnc5 jrs2 jrz4 inc2 jrc4 addi 5 0101 e abc e b2,rr,ee e y e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm 6 0110 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 inc 6 0110 e abc e b6,rr,ee e # e (x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 7 0111 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 ld 2 jrc 7 0111 e abc e b6,rr,ee e a,y e # 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 8 1000 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 ld 8 1000 e abc e b1,rr,ee e # e (x),a 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 9 1001 2 rnz 4 call 2 jrnc 5 jrs 2 jrz 4 inc 2 jrc 9 1001 e abc e b1,rr,ee e v e # 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc a 1010 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 and a 1010 e abc e b5,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind b 1011 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 ld 2 jrc 4 andi b 1011 e abc e b5,rr,ee e a,v e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm c 1100 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 sub c 1100 e abc e b3,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind d 1101 2 jrnz4 call2 jrnc5 jrs2 jrz4 inc2 jrc4 subi d 1101 e abc e b3,rr,ee e w e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm e 1110 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 dec e 1110 e abc e b7,rr,ee e # e (x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind f 1111 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 ld 2 jrc f 1111 e abc e b7,rr,ee e a,w e # 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc abbreviations for addressing modes: legend: dir direct # indicates illegal instructions sd short direct e 5 bit displacement imm immediate b 3 bit address inh inherent rr 1byte dataspace address ext extended nn 1 byte immediate data b.d bit direct abc 12 bit address bt bit test ee 8 bit displacement pcr program counter relative ind indirect 2 jrc e 1prc mnemonic addressing mode bytes cycle operand 62 47/70 st62t00c/t01c st62t03c/e01c opcode map summary (continued) low 8 1000 9 1001 a 1010 b 1011 c 1100 d 1101 e 1110 f 1111 low hi hi 0 0000 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 4 ldi 2 jrc 4 ld 0 0000 e abc e b0,rr e rr,nn e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 3 imm 1 prc 1 ind 1 0001 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 dec 2 jrc 4 ld 1 0001 e abc e b0,rr e x e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir 2 0010 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 4 com 2 jrc 4 cp 2 0010 e abc e b4,rr e a e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 prc 1 ind 3 0011 2 jrnz4 jp2 jrnc4 set2 jrz4 ld2 jrc4 cp 3 0011 e abc e b4,rr e x,a e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir 4 0100 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 2 reti 2 jrc 4 add 4 0100 e abc e b2,rr e e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind 5 0101 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 dec 2 jrc 4 add 5 0101 e abc e b2,rr e y e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir 6 0110 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 2 stop 2 jrc 4 inc 6 0110 e abc e b6,rr e e (y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind 7 0111 2 jrnz4 jp2 jrnc4 set2 jrz4 ld2 jrc4 inc 7 0111 e abc e b6,rr e y,a e rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir 8 1000 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 2 jrc 4 ld 8 1000 e abc e b1,rr e # e (y),a 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 prc 1 ind 9 1001 2 rnz 4 jp 2 jrnc 4 set 2 jrz 4 dec 2 jrc 4 ld 9 1001 e abc e b1,rr e v e rr,a 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir a 1010 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 4 rcl 2 jrc 4 and a 1010 e abc e b5,rr e a e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind b 1011 2 jrnz4 jp2 jrnc4 set2 jrz4 ld2 jrc4 and b 1011 e abc e b5,rr e v,a e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir c 1100 2 jrnz4 jp2 jrnc4 res2 jrz2 ret2 jrc4 sub c 1100 e abc e b3,rr e e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind d 1101 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 dec 2 jrc 4 sub d 1101 e abc e b3,rr e w e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir e 1110 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 2 wait 2 jrc 4 dec e 1110 e abc e b7,rr e e (y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind f 1111 2 jrnz4 jp2 jrnc4 set2 jrz4 ld2 jrc4 dec f 1111 e abc e b7,rr e w,a e rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir abbreviations for addressing modes: legend: dir direct # indicates illegal instructions sd short direct e 5 bit displacement imm immediate b 3 bit address inh inherent rr 1byte dataspace address ext extended nn 1 byte immediate data b.d bit direct abc 12 bit address bt bit test ee 8 bit displacement pcr program counter relative ind indirect 2 jrc e 1prc mnemonic addressing mode bytes cycle operand 63 48/70 st62t00c/t01c st62t03c/e01c 6 electrical characteristics 6.1 absolute maximum ratings this product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advisable to take normal precaution to avoid application of any voltage higher than the specified maximum rated voltages. for proper operation it is recommended that v i and v o be higher than v ss and lower than v dd . reliability is enhanced if unused inputs are con- nected to an appropriate logic voltage level (v dd or v ss ). power considerations .the average chip-junc- tion temperature, tj, in celsius can be obtained from: tj=ta + pd x rthja where:ta = ambient temperature. rthja =package thermal resistance (junc- tion-to ambient). pd = pint + pport. pint =idd x vdd (chip internal power). pport =port power dissipation (determined by the user). notes: - stresses above those listed as absolute maximum ratings may cause permanent damage to the device. this is a stress rating o nly and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended perio ds may affect device reliability. - (1) within these limits, clamping diodes are guarantee to be not conductive. voltages outside these limits are authorised as long as injection current is kept within the specification. symbol parameter value unit v dd supply voltage -0.3 to 7.0 v v i input voltage v ss - 0.3 to v dd + 0.3 (1) v v o output voltage v ss - 0.3 to v dd + 0.3 (1) v iv dd total current into v dd (source) 80 ma iv ss total current out of v ss (sink) 100 ma tj junction temperature 150 c t stg storage temperature -60 to 150 c 64 49/70 st62t00c/t01c st62t03c/e01c 6.2 recommended operating conditions notes : 1. care must be taken in case of negative current injection, where adapted impedance must be respected on analog sources to not affect the a/d conversion. for a -1ma injection, a maximum 10 k w is recommended. 2.an oscillator frequency above 1mhz is recommended for reliable a/d results figure 27. maximum operating frequency (fmax) versus supply voltage (v dd ) the shaded area is outside the recommended operating range; device functionality is not guaranteed under these conditions. symbol parameter test conditions value unit min. typ. max. t a operating temperature 6 suffix version 1 suffix version 3 suffix version -40 0 -40 85 70 125 c v dd operating supply voltage f osc = 4mhz, 1 & 6 suffix f osc = 4mhz, 3 suffix fosc= 8mhz , 1 & 6 suffix fosc= 8mhz , 3 suffix 3.0 3.0 3.6 4.5 6.0 6.0 6.0 6.0 v f osc oscillator frequency 2) v dd = 3.0v, 1 & 6 suffix v dd = 3.0v , 3 suffix v dd = 3.6v , 1 & 6 suffix v dd = 3.6v , 3 suffix 0 0 0 0 4.0 4.0 8.0 4.0 mhz i inj+ pin injection current (positive) v dd = 4.5 to 5.5v +5 ma i inj- pin injection current (negative) v dd = 4.5 to 5.5v -5 ma 8 7 6 5 4 3 2 1 2.5 3 4 4.5 5 5.5 6 supply voltage (v dd ) maximum frequency (mhz) functionality is not guaranteed in this area 3 suffix version 1 & 6 suffix version 3.6 65 50/70 st62t00c/t01c st62t03c/e01c 6.3 dc electrical characteristics (t a = -40 to +125c unless otherwise specified) notes: (1) hysteresis voltage between switching levels (2) all peripherals running (3) all peripherals in stand-by symbol parameter test conditions value unit min. typ. max. v il input low level voltage all input pins v dd x 0.3 v v ih input high level voltage all input pins v dd x 0.7 v v hys hysteresis voltage (1) all input pins v dd = 5v v dd = 3v 0.2 0.2 v v up lvd threshold in power-on 4.1 4.3 v dn lvd threshold in powerdown 3.5 3.8 v ol low level output voltage all output pins v dd = 5.0v; i ol = +10a v dd = 5.0v; i ol = + 3ma 0.1 0.8 v low level output voltage 20 ma sink i/o pins v dd = 5.0v; i ol = +10a v dd = 5.0v; i ol = +7ma v dd = 5.0v; i ol = +15ma 0.1 0.8 1.3 v oh high level output voltage all output pins v dd = 5.0v; i oh = -10a v dd = 5.0v; i oh = -3.0ma 4.9 3.5 v r pu pull-up resistance all input pins 40 100 350 kw reset pin 150 350 900 i il i ih input leakage current all input pins but reset v in = v ss (no pull-up configured) v in = v dd 0.1 1.0 m a input leakage current reset pin v in = v ss v in = v dd -8 -16 -30 10 i dd supply current in reset mode v reset =v ss f osc =8mhz 3.5 ma supply current in run mode (2) v dd =5.0v f int =8mhz 3.5 ma supply current in wait mode (3) v dd =5.0v f int =8mhz 1.5 ma supply current in stop mode, with lvd disabled (3) i load =0ma v dd =5.0v 20 m a supply current in stop mode, with lvd enabled (3) i load =0ma v dd =5.0v 500 retention eprom data retention t a = 55c 10 years 66 51/70 st62t00c/t01c st62t03c/e01c dc electrical characteristics (contd) (t a = -40 to +85c unless otherwise specified)) note: (*) all peripherals in stand-by. 6.4 ac electrical characteristics (t a = -40 to +125c unless otherwise specified) notes: 1. period for which v dd has to be connected at 0v to allow internal reset function at next power-up. 2 an oscillator frequency above 1mhz is recommended for reliable a/d results. 3. measure performed with oscin pin soldered on pcb, with an around 2pf equivalent capacitance. symbol parameter test conditions value unit min. typ. max. v up lvd threshold in power-on v dn +50 mv 4.1 4.3 v v dn lvd threshold in powerdown 3.6 3.8 v up -50 mv v v ol low level output voltage all output pins v dd = 5.0v; i ol = +10a v dd = 5.0v; i ol = + 5ma v dd = 5.0v; i ol = + 10mav 0.1 0.8 1.2 v low level output voltage 20 ma sink i/o pins v dd = 5.0v; i ol = +10a v dd = 5.0v; i ol = +10ma v dd = 5.0v; i ol = +20ma v dd = 5.0v; i ol = +30ma 0.1 0.8 1.3 2.0 v oh high level output voltage all output pins v dd = 5.0v; i oh = -10a v dd = 5.0v; i oh = -5.0ma 4.9 3.5 v i dd supply current in stop mode, with lvd disabled (*) i load =0ma v dd =5.0v 10 m a symbol parameter test conditions value unit min. typ. max. t rec supply recovery time (1) 100 ms f lfao internal frequency with lfao active 200 400 800 khz f osg internal frequency with osg enabled 2) v dd = 3v v dd = 3.6v v dd = 4.5v 2 2 4 f osc mhz f rc internal frequency with rc oscillator and osg disabled 2) 3) vdd=5.0v r=47k w r=100k w r=470k w 4 2.7 800 5 3.2 850 5.8 3.5 900 mhz mhz khz c in input capacitance all inputs pins 10 pf c out output capacitance all outputs pins 10 pf 67 52/70 st62t00c/t01c st62t03c/e01c 6.5 a/d converter characteristics (t a = -40 to +125c unless otherwise specified) notes : 1. noise at vdd, vss <10mv 2. with oscillator frequencies less than 1mhz, the a/d converter accuracy is decreased. 6.6 timer characteristics (t a = -40 to +125c unless otherwise specified) symbol parameter test conditions value unit min. typ. max. res resolution 8 bit a tot total accuracy (1) (2) f osc > 1.2mhz f osc > 32khz 2 4 lsb t c conversion time f osc = 8mhz (t a < 85c) f osc = 4 mhz 70 140 m s zir zero input reading conversion result when v in = v ss 00 hex fsr full scale reading conversion result when v in = v dd ff hex ad i analog input current during conversion v dd = 4.5v 1.0 m a ac in analog input capacitance 2 5 pf symbol parameter test conditions value unit min. typ. max. f in input frequency on timer pin mhz t w pulse width at timer pin v dd = 3.0v v dd > 4.5v 1 125 m s ns f int 4 --------- - 68 53/70 st62t00c/t01c st62t03c/e01c figure 28 . . rc frequency versus vcc figure 29. lvd thresholds versus temperature 33.544.555.56 0.1 1 10 mhz vdd (volts) frequency r=47k r=100k r=470k this curves represents typical variations and is given for guidance only 3.6 3.7 3.8 3.9 4 4.1 4.2 temp vthresh. -40c 25c 95c 125c vup vdn this curves represents typical variations and is given for guidance only 69 54/70 st62t00c/t01c st62t03c/e01c figure 30. idd wait versus vcc at 8 mhz for otp devices figure 31. idd stop versus vcc for otp devices figure 32. idd stop versus vcc for rom devices 0 0.2 0.4 0.6 0.8 1 1.2 vdd idd wait (ma) 3v 4v 5v 6v t = -40c t = 25c t = 95c t = 125c this curves represents typical variations and is given for guidance only -2 0 2 4 6 8 vdd idd wait (a) 3v 4v 5v 6v t = -40c t = 25c t = 95c t = 125c this curves represents typical variations and is given for guidance only -0.5 0 0.5 1 1.5 2 vdd idd stop (a) 3v 4v 5v 6v t = -40c t = 25c t = 95c t = 125c this curves represents typical variations and is given for guidance only 70 55/70 st62t00c/t01c st62t03c/e01c figure 33. idd wait versus vcc at 8mhz for rom devices figure 34. idd run versus vcc at 8 mhz for rom and otp devices figure 35. vol versus iol on all i/o port at vdd=5v 0 0.2 0.4 0.6 0.8 vdd idd wait (ma) 3v 4v 5v 6v t = -40c t = 25c t = 95c t = 125c this curves represents typical variations and is given for guidance only 1 2 3 4 5 vdd idd run (ma) 3v 4v 5v 6v t = -40c t = 25c t = 95c t = 125c this curves represents typical variations and is given for guidance only 010203040 0 2 4 6 8 iol (ma) vol (v) t = -40c t = 25c t = 95c t = 125c this curves represents typical variations and is given for guidance only 71 56/70 st62t00c/t01c st62t03c/e01c figure 36. vol versus iol on all i/o port at t=25c figure 37. vol versus iol for high sink (20ma) i/oports at t=25c figure 38. vol versus iol for high sink (20ma) i/o ports at vdd=5v 0 10203040 0 2 4 6 8 iol (ma) vol (v) vdd = 3.0v vdd = 4.0v vdd = 5.0v vdd = 6.0v this curves represents typical variations and is given for guidance only 0 10203040 0 1 2 3 4 5 iol (ma) vol (v) vdd = 3.0v vdd = 4.0v vdd = 5.0v vdd = 6.0v this curves represents typical variations and is given for guidance only 0 10203040 0 1 2 3 4 5 iol (ma) vol (v) t = -40c t = 25c t = 95c t = 125c this curves represents typical variations and is given for guidance only 72 57/70 st62t00c/t01c st62t03c/e01c figure 39. voh versus ioh on all i/o port at 25c figure 40. voh versus ioh on all i/o port at vdd=5v 0 10203040 -2 0 2 4 6 ioh (ma) voh (v) vdd = 3.0v vdd = 4.0v vdd = 5.0v vdd = 6.0v this curves represents typical variations and is given for guidance only 0 10203040 -2 0 2 4 6 ioh (ma) voh (v) t = -40c t = 25c t = 95c t = 125c this curves represents typical variations and is given for guidance only 73 58/70 st62t00c/t01c st62t03c/e01c 7 general information 7.1 package mechanical data figure 41. 16-pin plastic dual in line package (b), 300-mil width figure 42. 16-pin ceramic side-brazed dual in-line package dim. mm inches min typ max min typ max a 5.33 0.210 a1 0.38 0.015 a2 2.92 3.30 4.95 0.115 0.130 0.195 b 0.36 0.56 0.014 0.022 b2 1.52 1.78 0.060 0.070 c 0.20 0.25 0.36 0.008 0.010 0.014 d 18.67 19.18 19.69 0.735 0.755 0.775 e 2.54 0.100 e1 6.10 6.35 7.11 0.240 0.250 0.280 l 2.92 3.30 3.81 0.115 0.130 0.150 number of pins n 16 pdip16 dim. mm inches min typ max min typ max a 3.78 0.149 a1 0.38 0.015 b 0.36 0.46 0.56 0.014 0.018 0.022 b1 1.14 1.37 1.78 0.045 0.054 0.070 c 0.20 0.25 0.36 0.008 0.010 0.014 d 19.86 20.32 20.78 0.782 0.800 0.818 d1 17.78 0.700 e1 7.04 7.49 7.95 0.277 0.295 0.313 e 2.54 0.100 g 6.35 6.60 6.86 0.250 0.260 0.270 g1 9.47 9.73 9.98 0.373 0.383 0.393 g2 1.02 0.040 l 2.92 3.30 3.81 0.115 0.130 0.150 s 1.27 0.050 ? 4.22 0.166 number of pins n16 cdip16w 74 59/70 st62t00c/t01c st62t03c/e01c package mechanical data (contd) figure 43. 16-pin plastic small outline package (m), 300-mil width 7.2 ordering information table 18. otp/eprom version ordering information sales type i/o program memory (bytes) analog input temperature range package st62t00cb6 9 1036 (otp) 4 -40 to + 85c pdip16 st62t00cm6 pso16 ST62T01Cb6 1836 (otp) pdip16 ST62T01Cm6 pso16 st62t03cb6 1036 (otp) none pdip16 st62t03cm6 pso16 ST62T01Cb3 1836 (otp) -40 to +125c pdip16 ST62T01Cm3 pso16 st62e01cf1 1836(eprom) 4 0 to +70c cdip16w dim. mm inches min typ max min typ max a 2.35 2.65 0.0926 0.1043 a1 0.10 0.0040 b 0.33 0.51 0.013 0.020 c 0.32 0.0125 d 10.10 10.50 0.3977 0.4133 e 7.40 7.60 0.2914 0.2992 e 1.27 0.050 h 10.01 10.64 0.394 0.419 h 0.25 0.74 0.010 0.029 k 0 8 0 8 l 0.41 1.27 0.016 0.050 g 0.10 0.004 number of pins n16 so16 75 60/70 st62t00c/t01c st62t03c/e01c notes: 76 september 1998 61/70 rev. 2.6 st62p00c/p01c/p03c 8-bit fastrom mcus with a/d converter, oscillator safeguard , safe reset and 16 pins n 3.0 to 6.0v supply operating range n 8 mhz maximum clock frequency n -40 to +125c operating temperature range n run, wait and stop modes n 5 interrupt vectors n look-up table capability in program memory n data storage in program memory: user selectable size n data ram: 64bytes n 9 i/o pins, fully programmable as: C input with pull-up resistor C input without pull-up resistor C input with interrupt generation C open-drain or push-pull output C analog input (except st62p03c) n 3 i/o lines can sink up to 20ma to drive leds or triacs directly n 8-bit timer/counter with 7-bit programmable prescaler n digital watchdog n oscillator safe guard n low voltage detector for safe reset n 8-bit a/d converter with up to 4 analog inputs n on-chip clock oscillator can be driven by quartz crystal ceramic resonator or rc network n power-on reset n one external non-maskable interrupt n st626x-emu2 emulation and development system (connects to an ms-dos pc via a parallel port) device summary (see end of datasheet for ordering information) pdip16 pso16 device rom (bytes) i/o pins analog inputs st62p00c 1036 9 4 st62p01c 1836 9 4 st62p03c 1036 9 none 77 62/70 st62p00c/p01c/p03c 1 general description 1.1 introduction the st62p00c/p01c and p03c are the f actory a dvanced s ervice t echnique rom (fastrom) versions of st62t00c,t01c and t03c otp devic- es. they offer the same functionality as otp devices, selecting as fastrom options the options de- fined in the programmable option byte of the otp version. 1.2 ordering information the following section deals with the procedure for transfer of customer codes to stmicroelectronics. 1.2.1 transfer of customer code customer code is made up of the rom contents and the list of the selected fastrom options. the rom contents are to be sent on diskette, or by electronic means, with the hexadecimal file generated by the development tool. all unused bytes must be set to ffh. the selected options are communicated to stmi- croelectronics using the correctly filled option list appended. 1.2.2 listing generation and verification when stmicroelectronics receives the users rom contents, a computer listing is generated from it. this listing refers exactly to the rom con- tents and options which will be used to produce the specified mcu. the listing is then returned to the customer who must thoroughly check, com- plete, sign and return it to stmicroelectronics. the signed listing forms a part of the contractual agree- ment for the production of the specific customer mcu. the stmicroelectronics sales organization will be pleased to provide detailed information on con- tractual points. table 1. rom memory map for st62p00c,p03c table 2. rom memory map for st62p01c table 3. fastrom version ordering information (*) advanced information device address description 0000h-0b9fh 0ba0h-0f9fh 0fa0h-0fefh 0ff0h-0ff7h 0ff8h-0ffbh 0ffch-0ffdh 0ffeh-0fffh reserved user rom reserved interrupt vectors reserved nmi interrupt vector reset vector device address description 0000h-087fh 0880h-0f9fh 0fa0h-0fefh 0ff0h-0ff7h 0ff8h-0ffbh 0ffch-0ffdh 0ffeh-0fffh reserved user rom reserved interrupt vectors reserved nmi interrupt vector reset vector sales type rom analog inputs temperature range package st62p00cb1/xxx st62p00cb6/xxx st62p00cb3/xxx (*) 1036 bytes 4 0 to +70c -40 to + 85c -40 to + 125c pdip16 st62p00cm1/xxx st62p00cm6/xxx st62p00cm3/xxx (*) 0 to +70c -40 to + 85c -40 to + 125c pso16 st62p01cb1/xxx st62p01cb6/xxx st62p01cb3/xxx (*) 1836 bytes 0 to +70c -40 to + 85c -40 to + 125c pdip16 st62p01cm1/xxx st62p01cm6/xxx st62p01cm3/xxx (*) 0 to +70c -40 to + 85c -40 to + 125c pso16 st62p03cb1/xxx st62p03cb6/xxx st62p03cb3/xxx (*) 1036 bytes none 0 to +70c -40 to + 85c -40 to + 125c pdip16 st62p03cm1/xxx st62p03cm6/xxx st62p03cm3/xxx (*) 0 to +70c -40 to + 85c -40 to + 125c pso16 78 63/70 st62p00c/p01c/p03c st62p00c/p01c/p03c fastrom microcontroller option list customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone no . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . stmicroelectronics references device: [ ] st62p00c [ ] st62p01c [ ] st62p03c package: [ ] dual in line plastic [ ] small outline plastic with conditionning: [ ] standard (stick) [ ] tape & reel temperature range: [ ] 0c to + 70c [ ] - 40c to + 85c [ ] - 40c to + 125c oscillator source selection: [ ] crystal quartz/ceramic resonator [ ] rc network watchdog selection: [ ] software activation [ ] hardware activation readout protection: [ ] disabled [ ] enabled external stop mode control[ ] enabled [ ] disabled lvd reset [ ] enabled [ ] disabled nmi pin pull-up [ ] enabled [ ] disabled osg [ ] enabled [ ] disabled comments : supply operating range in the application: oscillator fequency in the application: notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . date . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 64/70 st62p00c/p01c/p03c notes: 80 september 1998 65/70 rev. 2.6 st6200c/01c/03c 8-bit rom mcus with a/d converter, oscillator safeguard , safe reset and 16 pins n 3.0 to 6.0v supply operating range n 8 mhz maximum clock frequency n -40 to +125c operating temperature range n run, wait and stop modes n 5 interrupt vectors n look-up table capability in program memory n data storage in program memory: user selectable size n data ram: 64bytes n 9 i/o pins, fully programmable as: C input with pull-up resistor C input without pull-up resistor C input with interrupt generation C open-drain or push-pull output C analog input (except st6203c) n 3 i/o lines can sink up to 20ma to drive leds or triacs directly n 8-bit timer/counter with 7-bit programmable prescaler n digital watchdog n oscillator safe guard n low voltage detector for safe reset n 8-bit a/d converter with up to 4 analog inputs n on-chip clock oscillator can be driven by quartz crystal ceramic resonator or rc network n power-on reset n one external non-maskable interrupt n st626x-emu2 emulation and development system (connects to an ms-dos pc via a parallel port) device summary (see end of datasheet for ordering information) pdip16 pso16 device rom (bytes) i/o pins analog inputs st6200c 1036 9 4 st6201c 1836 9 4 st6203c 1036 9 none 81 66/70 st6200c/01c/03c 1 general description 1.1 introduction the st6200c/01c and 03c are mask pro- grammed rom version of st62t00c,t01c and t03c otp devices. they offer the same functionality as otp devices, selecting as rom options the options defined in the programmable option byte of the otp version. figure 1. programming wave form 1.2 rom readout protection if the rom readout protection option is selected, a protection fuse can be blown to pre- vent any access to the program memory content. in case the user wants to blow this fuse, high volt- age must be applied on the test pin. figure 2. programming circuit note: zpd15 is used for overvoltage protection 0.5s min test 15 14v typ 10 5 test 100ma 4ma typ vr02001 max 150 s typ t vr02003 test 5v 100nf 47mf protect 100nf v dd v ss zpd15 15v 14v 82 67/70 st6200c/01c/03c st6200c/01c/03c microcontroller option list customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone no . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . stmicroelectronics references device: [ ] st6200c [ ] st6201c [ ] st6203c package: [ ] dual in line plastic [ ] small outline plastic with conditionning: [ ] standard (stick) [ ] tape & reel temperature range: [ ] 0c to + 70c [ ] - 40c to + 85c [ ] - 40c to + 125c special marking: [ ] no [ ] yes "_ _ _ _ _ _ _ _ _ _ _ " authorized characters are letters, digits, '.', '-', '/' and spaces only. maximum character count: dip16: 9 so16: 6 oscillator source selection: [ ] crystal quartz/ceramic resonator [ ] rc network watchdog selection: [ ] software activation [ ] hardware activation rom readout protection: [ ] disabled (fuse cannot be blown) [ ] enabled (fuse can be blown by the customer) note: no part is delivered with protected rom. the fuse must be blown for protection to be effective. external stop mode control[ ] enabled [ ] disabled lvd reset [ ] enabled [ ] disabled nmi pin pull-up [ ] enabled [ ] disabled osg [ ] enabled [ ] disabled comments : supply operating range in the application: oscillator fequency in the application: notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . date . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 68/70 st6200c/01c/03c 1.3 ordering information the following section deals with the procedure for transfer of customer codes to stmicroelectronics. 1.3.1 transfer of customer code customer code is made up of the rom contents and the list of the selected mask options. the rom contents are to be sent on diskette, or by electronic means, with the hexadecimal file gener- ated by the development tool. all unused bytes must be set to ffh. the selected mask options are communicated to stmicroelectronics using the correctly filled op- tion list appended. 1.3.2 listing generation and verification when stmicroelectronics receives the users rom contents, a computer listing is generated from it. this listing refers exactly to the mask which will be used to produce the specified mcu. the listing is then returned to the customer who must thoroughly check, complete, sign and return it to stmicroelectronics. the signed listing forms a part of the contractual agreement for the creation of the specific customer mask. the stmicroelectronics sales organization will be pleased to provide detailed information on con- tractual points. table 4. rom memory map for st6200c,03c table 5. rom memory map for st6201c device address description 0000h-0b9fh 0ba0h-0f9fh 0fa0h-0fefh 0ff0h-0ff7h 0ff8h-0ffbh 0ffch-0ffdh 0ffeh-0fffh reserved user rom reserved interrupt vectors reserved nmi interrupt vector reset vector device address description 0000h-087fh 0880h-0f9fh 0fa0h-0fefh 0ff0h-0ff7h 0ff8h-0ffbh 0ffch-0ffdh 0ffeh-0fffh reserved user rom reserved interrupt vectors reserved nmi interrupt vector reset vector 84 69/70 st6200c/01c/03c ordering information (contd) table 6. rom version ordering information sales type rom analog inputs temperature range package st6200cb1/xxx st6200cb6/xxx st6200cb3/xxx 1036 bytes 4 0 to +70c -40 to + 85c -40 to + 125c pdip16 st6200cm1/xxx st6200cm6/xxx st6200cm3/xxx 0 to +70c -40 to + 85c -40 to + 125c pso16 st6201cb1/xxx st6201cb6/xxx st6201cb3/xxx 1836 bytes 0 to +70c -40 to + 85c -40 to + 125c pdip16 st6201cm1/xxx st6201cm6/xxx st6201cm3/xxx 0 to +70c -40 to + 85c -40 to + 125c pso16 st6203cb1/xxx st6203cb6/xxx st6203cb3/xxx 1036 bytes none 0 to +70c -40 to + 85c -40 to + 125c pdip16 st6203cm1/xxx st6203cm6/xxx st6203cm3/xxx 0 to +70c -40 to + 85c -40 to + 125c pso16 85 70/70 st6200c/01c/03c notes: information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroele ctronics. the st logo is a registered trademark of stmicroelectronics ? 1998 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the neth erlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com 86 |
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